Quality is an important measurement within a semiconductor manufactory. Due to the fact that yield is directly affected by quality of the manufacturing process, in this paper a quality based scheduling approach will be presented which compares different methods like dispatching, MIP and CP, regarding different objectives. To test the different used methods a benchmark model of a semiconductor manufactory is build up. Here a lithography work center is used in detail where the rest of the fabrication is only build up as a delay station. With this model the repeatability for the example of a lithography step is investigated. Thereby in this investigation it is assumed, that each lithography tool has an offset which is transferred to the structure. Now the quality of a product should be best, if the offset from one layer to the next layer is minimized.

Der technologische Fortschritt gestattet die Implementierung zunehmend komplexerer Prozessorarchitekturen auf einem Schaltkreis. Ein Trend der letzten Jahre ist die Implementierung von mehr und mehr Verarbeitungseinheiten auf einem Chip. Daraus ergeben sich neue Herausforderungen für die Abbildung von Algorithmen auf solche Architekturen, denn alle Verarbeitungseinheiten sollen effizient bei der Ausführung des Algorithmus genutzt werden. Der Schwerpunkt der eingereichten Dissertation ist die Ausnutzung der Parallelität von Rechenfeldern mit Teilwortparallelität. Solche Architekturen erlauben Parallelverarbeitung auf mehreren Ebenen. Daher wurde eine Abbildungsstrategie, mit besonderem Schwerpunkt auf Teilwortparallelität entwickelt. Diese Abbildungsstrategie basiert auf den Methoden des Rechenfeldentwurfs. Rechenfelder sind regelmäßig angeordnete Prozessorelemente, die nur mit ihren Nachbarelementen kommunizieren. Die Datenein- und -ausgabe wird durch die Prozessorelemente am Rand des Rechenfeldes realisiert. Jedes Prozessorelement kann mehrere Funktionseinheiten besitzen, welche die Rechenoperationen des Algorithmus ausführen. Die Teilwortparallelität bezeichnet die Fähigkeit zur Teilung des Datenpfads der Funktionseinheit in mehrere schmale Datenpfade für die parallele Ausführung von Daten mit geringer Wortbreite. Die entwickelte Abbildungsstrategie unterteilt sich in zwei Schritte, die \"Vorverarbeitung\" und die \"Mehrstufige Modifizierte Copartitionierung\" (kurz: MMC). Die \"Vorverarbeitung\" verändert den Algorithmus in einer solchen Art, dass der veränderte Algorithmus schnell und effizient auf die Zielarchitektur abgebildet werden kann. Hierfür wurde ein Optimierungsproblem entwickelt, welches schrittweise die Parameter für die Transformation des Algorithmus bestimmt. Die \"Mehrstufige Modifizierte Copartitionierung\" wird für die schrittweise Anpassung des Algorithmus an die Zielarchitektur eingesetzt. Darüber hinaus ermöglicht die Abbildungsmethode die Ausnutzung der lokalen Register in den Prozessorelementen und die Anpassung des Algorithmus an die Speicherarchitektur, an die das Rechenfeld angebunden ist. Die erste Stufe der MMC dient der Transformation eines Algorithmus mit Einzeldatenoperationen in einen Algorithmus mit teilwortparallelen Operationen. Mit der zweiten Copartitionierungsstufe wird der Algorithmus an die lokalen Register und an das Rechenfeld angepasst. Weitere Copartitionierungsstufen können zur Anpassung des Algorithmus an die Speicherarchitektur verwendet werden. / The technological progress allows the implementation of complex processor architectures on a chip. One trend of the last years is the implemenation of more and more execution units on one chip. That implies new challenges for the mapping of algorithms on such architectures, because the execution units should be used efficiently during the execution of the algorithm. The focus of the submitted dissertation thesis is the utilization of the parallelism of processor arrays with subword parallelism. Such architectures allow parallel executions on different levels. Therefore an algorithm mapping strategy was developed, where the exploitation of the subword parallelism was in the focus. This algorithm mapping strategy is based on the methods of the processor array design. Processor arrays are regular arranged processor elements, which communicate with their neighbors elements only. The data in- and output will be realized by the processor elements on the border of the array. Each processor element can have several functional units, which execute the computational operations. Subword parallelism means the capability for splitting the data path of the functional units in several smaller chunks for the parallel execution of data with lower word width. The developed mapping strategy is subdivided in two steps, the \"Preprocessing\" and the \"Multi-Level Modified Copartitioning\" (kurz: MMC), whereat the MMC means the method of the step simultaneously. The \"Preprocessing\" alter the algorithm in such a kind, that the altered algorithm can be fast and efficient mapped on the target architecture. Therefore an optimization problem was developed, which determines gradual the parameter for the transformation of the algorithm. The \"Multi-Level Modified Copartitioning\" is used for mapping the algorithm gradual on the target architecture. Furthermore the mapping methodology allows the exploitation of the local registers in the processing elements and the adaptation of the algorithm on the memory architecture, where the processing array is connected on. The first level of the MMC is used for the transformation of an algorithm with operation based on single data to an algorithm with subword parallel operations. With the second level, the algorithm will be adapted to the local registers in the processing elements and to the processor array. Further copartition levels can be used for matching the algorithm to the memory architecture.

Techn. Hochsch., Diss--Aachen, 2005.

Universiẗat, Diss--Hamburg, 2006.

Only if humanity acts quickly and resolutely can we limit global warming' conclude more than 25,000 academics with the statement of SCIENTISTS FOR FUTURE. The concern about global warming and the extinction of species has steadily increased in recent years.

Es wird ein Ansatz zur zeitbeschränkten Ablaufplanung für VLIW-Prozessoren mit neuronalen Netzen vorgestellt. Bestehende Arbeiten werden dahingehend erweitert, dass der Datenpfad des Prozessors über heterogene funktionale Einheiten verfügen und geclustert sein darf. Es werden zwei Varianten zur Lösung des Problems angegeben, deren Qualität mit einem heuristischen Ansatz verglichen wird und Schlussfolgerungen bezüglich der Nutzbarkeit neuronaler Netze gezogen.

Coal is a fossil fuel mineral, which is presently a major source of electricity and energy to industries. From past to present, there are many coal reserves around the world and large scale coal mining operates in various areas such as the USA, Russia, China, Australia, India, and Germany, etc. Thailand’s coal resources can be found in many areas; there are lignite mining in the north of Thailand, the currently operational Mae Moh Lignite Mine, and also coal reserves in the south of Thailand, such as Krabi and Songkhla, where mines are not yet operating. The main consumption of coal is in electricity production, which increases annually. In 2019, the Thai Government and Electricity Generating Authority of Thailand (EGAT) plans to run a 800 MW coal power plant at Krabi, which may run on imported coal, despite there being reserves of lignite at Krabi; the use of domestic coal is a last option because of social and environmental concerns about the effects of coal mining. There is a modern trend in mining projects, the responsibility of mining should cover not only the mining activity, but the social and environmental protection and mine closure activities which follow. Thus, the costs and decisions taken on by the mining company are increasingly complicated. To reach a decision on investment in a mining project is not easy; it is a complex process in which all variables are connected. Particularly, the responsibility of coal mining companies to society and the environment is a new topic. Thus, a tool to help to recognize and generate information for decision making is in demand and very important. In this thesis, the system dynamics model of coal mine planning is made by using Vensim Software and specifically designed to encompass many variables during the period of mining activity until the mine closure period. The decisions use economic criteria such as Net Present Value (NPV), Net Cash Flow (NCF), Payback Period (PP), and Internal Rate of Return (IRR), etc. Consequently, the development of the decision support system of coal mine planning as a tool is proposed. The model structure covers the coal mining area from mine reserves to mine closure. It is a fast and flexible tool to perform sensitivity analysis, and to determine an optimum solution. The model results are clear and easily understandable on whether to accept or reject the coal mine project, which helps coal mining companies make the right decisions on their policies, economics, and the planning of new coal mining projects. Furthermore, the model is used to analyse the case study of the Krabi coal-fired power plant in Thailand, which may possibly use the domestic lignite at Krabi. The scenario simulations clearly show some potential for the use of the domestic lignite. However, the detailed analysis of the Krabi Lignite Mine Project case shows the high possible risks of this project, and that this project is currently not feasible. Thus, the model helps to understand and confirm that the use of domestic lignite in Krabi for the Krabi Coal Power Plant Project is not suitable at this time. Therefore, the best choice is imported coal from other countries for supporting the Krabi Coal Power Plant Project. Finally, this tool successfully is a portable application software, which does not need to be installed on a computer, but can run directly in a folder of the existing application. Furthermore, it supports all versions of Windows OS.

Coal is a fossil fuel mineral, which is presently a major source of electricity and energy to industries. From past to present, there are many coal reserves around the world and large scale coal mining operates in various areas such as the USA, Russia, China, Australia, India, and Germany, etc. Thailand’s coal resources can be found in many areas; there are lignite mining in the north of Thailand, the currently operational Mae Moh Lignite Mine, and also coal reserves in the south of Thailand, such as Krabi and Songkhla, where mines are not yet operating. The main consumption of coal is in electricity production, which increases annually. In 2019, the Thai Government and Electricity Generating Authority of Thailand (EGAT) plans to run a 800 MW coal power plant at Krabi, which may run on imported coal, despite there being reserves of lignite at Krabi; the use of domestic coal is a last option because of social and environmental concerns about the effects of coal mining. There is a modern trend in mining projects, the responsibility of mining should cover not only the mining activity, but the social and environmental protection and mine closure activities which follow. Thus, the costs and decisions taken on by the mining company are increasingly complicated. To reach a decision on investment in a mining project is not easy; it is a complex process in which all variables are connected. Particularly, the responsibility of coal mining companies to society and the environment is a new topic. Thus, a tool to help to recognize and generate information for decision making is in demand and very important. In this thesis, the system dynamics model of coal mine planning is made by using Vensim Software and specifically designed to encompass many variables during the period of mining activity until the mine closure period. The decisions use economic criteria such as Net Present Value (NPV), Net Cash Flow (NCF), Payback Period (PP), and Internal Rate of Return (IRR), etc. Consequently, the development of the decision support system of coal mine planning as a tool is proposed. The model structure covers the coal mining area from mine reserves to mine closure. It is a fast and flexible tool to perform sensitivity analysis, and to determine an optimum solution. The model results are clear and easily understandable on whether to accept or reject the coal mine project, which helps coal mining companies make the right decisions on their policies, economics, and the planning of new coal mining projects. Furthermore, the model is used to analyse the case study of the Krabi coal-fired power plant in Thailand, which may possibly use the domestic lignite at Krabi. The scenario simulations clearly show some potential for the use of the domestic lignite. However, the detailed analysis of the Krabi Lignite Mine Project case shows the high possible risks of this project, and that this project is currently not feasible. Thus, the model helps to understand and confirm that the use of domestic lignite in Krabi for the Krabi Coal Power Plant Project is not suitable at this time. Therefore, the best choice is imported coal from other countries for supporting the Krabi Coal Power Plant Project. Finally, this tool successfully is a portable application software, which does not need to be installed on a computer, but can run directly in a folder of the existing application. Furthermore, it supports all versions of Windows OS.

Der technologische Fortschritt gestattet die Implementierung zunehmend komplexerer Prozessorarchitekturen auf einem Schaltkreis. Ein Trend der letzten Jahre ist die Implementierung von mehr und mehr Verarbeitungseinheiten auf einem Chip. Daraus ergeben sich neue Herausforderungen für die Abbildung von Algorithmen auf solche Architekturen, denn alle Verarbeitungseinheiten sollen effizient bei der Ausführung des Algorithmus genutzt werden. Der Schwerpunkt der eingereichten Dissertation ist die Ausnutzung der Parallelität von Rechenfeldern mit Teilwortparallelität. Solche Architekturen erlauben Parallelverarbeitung auf mehreren Ebenen. Daher wurde eine Abbildungsstrategie, mit besonderem Schwerpunkt auf Teilwortparallelität entwickelt. Diese Abbildungsstrategie basiert auf den Methoden des Rechenfeldentwurfs. Rechenfelder sind regelmäßig angeordnete Prozessorelemente, die nur mit ihren Nachbarelementen kommunizieren. Die Datenein- und -ausgabe wird durch die Prozessorelemente am Rand des Rechenfeldes realisiert. Jedes Prozessorelement kann mehrere Funktionseinheiten besitzen, welche die Rechenoperationen des Algorithmus ausführen. Die Teilwortparallelität bezeichnet die Fähigkeit zur Teilung des Datenpfads der Funktionseinheit in mehrere schmale Datenpfade für die parallele Ausführung von Daten mit geringer Wortbreite. Die entwickelte Abbildungsstrategie unterteilt sich in zwei Schritte, die \"Vorverarbeitung\" und die \"Mehrstufige Modifizierte Copartitionierung\" (kurz: MMC). Die \"Vorverarbeitung\" verändert den Algorithmus in einer solchen Art, dass der veränderte Algorithmus schnell und effizient auf die Zielarchitektur abgebildet werden kann. Hierfür wurde ein Optimierungsproblem entwickelt, welches schrittweise die Parameter für die Transformation des Algorithmus bestimmt. Die \"Mehrstufige Modifizierte Copartitionierung\" wird für die schrittweise Anpassung des Algorithmus an die Zielarchitektur eingesetzt. Darüber hinaus ermöglicht die Abbildungsmethode die Ausnutzung der lokalen Register in den Prozessorelementen und die Anpassung des Algorithmus an die Speicherarchitektur, an die das Rechenfeld angebunden ist. Die erste Stufe der MMC dient der Transformation eines Algorithmus mit Einzeldatenoperationen in einen Algorithmus mit teilwortparallelen Operationen. Mit der zweiten Copartitionierungsstufe wird der Algorithmus an die lokalen Register und an das Rechenfeld angepasst. Weitere Copartitionierungsstufen können zur Anpassung des Algorithmus an die Speicherarchitektur verwendet werden. / The technological progress allows the implementation of complex processor architectures on a chip. One trend of the last years is the implemenation of more and more execution units on one chip. That implies new challenges for the mapping of algorithms on such architectures, because the execution units should be used efficiently during the execution of the algorithm. The focus of the submitted dissertation thesis is the utilization of the parallelism of processor arrays with subword parallelism. Such architectures allow parallel executions on different levels. Therefore an algorithm mapping strategy was developed, where the exploitation of the subword parallelism was in the focus. This algorithm mapping strategy is based on the methods of the processor array design. Processor arrays are regular arranged processor elements, which communicate with their neighbors elements only. The data in- and output will be realized by the processor elements on the border of the array. Each processor element can have several functional units, which execute the computational operations. Subword parallelism means the capability for splitting the data path of the functional units in several smaller chunks for the parallel execution of data with lower word width. The developed mapping strategy is subdivided in two steps, the \"Preprocessing\" and the \"Multi-Level Modified Copartitioning\" (kurz: MMC), whereat the MMC means the method of the step simultaneously. The \"Preprocessing\" alter the algorithm in such a kind, that the altered algorithm can be fast and efficient mapped on the target architecture. Therefore an optimization problem was developed, which determines gradual the parameter for the transformation of the algorithm. The \"Multi-Level Modified Copartitioning\" is used for mapping the algorithm gradual on the target architecture. Furthermore the mapping methodology allows the exploitation of the local registers in the processing elements and the adaptation of the algorithm on the memory architecture, where the processing array is connected on. The first level of the MMC is used for the transformation of an algorithm with operation based on single data to an algorithm with subword parallel operations. With the second level, the algorithm will be adapted to the local registers in the processing elements and to the processor array. Further copartition levels can be used for matching the algorithm to the memory architecture.