This thesis focuses on the logical design of binary adders. It covers topics extending from cardinal numbers to carry skip optimization. The conventional adder designs are described in detail, including: carry completion, ripple carry, carry select, carry skip, conditional sum, and carry lookahead. We show that the method of parallel prefix analysis can be used to unify the conventional adder designs under one parameterized model. The parallel prefix model also produces other useful configurations, and can be used with carry operator variations that are associative. Parallel prefix adder parameters include group sizes, tree shape, and device sizes. We also introduce a general algorithm for group size optimization. Code for this algorithm is available on the World Wide Web. Finally, the thesis shows the derivation for some carry operator variations including those originally given by Majerski and Ling. / text

Significant characteristic of any VLSI design circuit is its power, reliability, operating frequency and implementation cost. Dynamic CMOS designs provide high operating speeds compared to static CMOS designs combined with low silicon area requirement. This thesis describes the design and the optimization of high performance carry select adder. Previous researchers believed that existing CSA designs has reached theoretical speed bound. But, only a considerable portion of hardware resources of traditional adders are used in worst case scenario. Based on this observation our proposed design will improve on theoretical limit. The major scope of this proposed design is to increase the speed of carry generation between intermediate blocks of Carry select Adder (CSA) by introducing fast multiple clock Domino Manchester carry chain (MCC) that generates carry outputs. This design technique will have some advantages compared to pre-existing implementations in operating speed and power delay product. Simulation has been done using GPDK (Generic Process Design Kits) technology using cadence virtuoso. Thus the proposed technique provides advantages over pre-existing techniques in terms of operating speed.