Built with nanomagnets, a spintronic device called the all-spin logic (ASL) device carries information with only spin currents, resulting in a low power supply--10 mV. This voltage is 100 times smaller than the conventional CMOS devices (usually 0.8~1V). The potential for improved energy efficiency made possible by the low operating voltage of ASL makes it one of the most promising devices among its post-CMOS competitors. The basic working principles of ASL device are introduced in this thesis and two complementary approaches to studying energy efficiency of computation are applied to a common set of ASL circuits: (1) a circuit simulation approach that provides efficiency estimates for specific ASL circuit realizations, and (2) a physical-information-theoretic approach that reveals fundamental efficiency bounds for ASL circuits as limited by irreversible information loss. The results of this study support the expectation that the energy efficiency of computation in ASL can far exceed that of CMOS. However, it also reveals that ASL efficiencies--shown to exceed fundamental limits by many orders of magnitude in the ASL implementations studied here--are unlikely to approach fundamental limits because of the unavoidable energetic overhead cost of maintaining spin currents.

With the aggressive scaling of complementary metal-oxide semiconductor (CMOS) nearing an inevitable physical limit and its well-known power crisis, the quest for an alternative/augmenting technology that surpasses the current semiconductor electronics is needed for further technological progress. Spintronic devices emerge as prime candidates for Beyond CMOS era by utilizing the electron spin as an extra degree of freedom to decrease the power consumption and overcome the velocity limit connected with the charge. By using the nonvolatility nature of magnetization along with its direction to represent a bit of information and then manipulating it by spin-polarized currents, routes are opened for combined memory and logic. This would not have been possible without the recent discoveries in the physics of nanomagnetism such as spin-transfer torque (STT) whereby a spin-polarized current can excite magnetization dynamics through the transfer of spin angular momentum. STT have expanded the available means of switching the magnetization of magnetic layers beyond old classical techniques, promising to fulfill the need for a new generation of dense, fast, and nonvolatile logic and storage devices. All-spin logic (ASL) is among the most promising spintronic logic switches due to its low power consumption, logic-in-memory structure, and operation on pure spin currents. The device is based on a lateral nonlocal spin valve and STT switching. It utilizes two nanomagnets (whereby information is stored) that communicate with pure spin currents through a spin-coherent nonmagnetic channel. By using the well-known spin physics and the recently proposed four-component spin circuit formalism, ASL can be thoroughly studied and simulated. Previous attempts to model ASL in the linear and diffusive regime either neglect the dynamic characteristics of transport or do not provide a scalable and robust platform for full micromagnetic simulations and inclusion of other effects like spin Hall effect and spin-orbit torque. In this thesis, we propose an improved stochastic magnetization dynamics/time-dependent spin transport model based on a finite-difference scheme of both the temporal and spatial derivatives to capture the key features of ASL. The approach yields new finite-difference conductance matrices, which, in addition to recovering the steady-state results, captures the dynamic behavior. The new conductance matrices are general in that the discretization framework can be readily applied and extended to other spintronic devices. Also, we provide a stable algorithm that can be used to simulate a generic ASL switch using the developed model.

La technologie CMOS a contribué au développement de l'industrie des semi-conducteurs. Cependant, au fur et à mesure que le noeud technologique est réduit, la technologie CMOS fait face à des défis importants liés à la dissipation dûe aux courants de fuite et aux effets du canal court. Pour résoudre ce problème, les chercheurs se sont intéressés à la spintronique ces dernières années, compte tenu de la possibilité de fabriquer des dispositifs de taille réduite et d'opérations de faible puissance. La jonction tunnel magnétique (MTJ) est l'un des dispositifs spintroniques les plus importants qui peut stocker des données binaires grâce à la Magnétorésistance à effet tunnel (TMR). En dehors des applications de mémoire non volatile, la MTJ peut également être utilisée pour combiner ou remplacer les circuits CMOS pour implémenter un circuit hybride, de façon à combiner une faible consommation d'énergie et des performances à grande vitesse. Cependant, le problème de la conversion fréquente de charge en spin dans un circuit hybride peut entraîner une importante consommation d'énergie, ce qui obère l'intérêt pour des circuits hybrides. Par conséquent, le concept ASL qui repose sur un pur courant de spin comme support de l'information est proposé pour limiter les conversions entre charge et spin, donc pour réduire la consommation d'énergie. La conception de circuits à base de dispositif ASL entraîne de nombreux défis liés à l'hétérogénéité qu'ils introduisent et à l'espace de conception étendu à explorer. Par conséquent, cette thèse se concentre sur l'écart entre les exigences d'application au niveau du système et la fabrication des nanodispositifs. Au niveau du dispositif, nous avons développé un modèle compact intégrant le STT, la TMR, les effets d'injection/accumulation de spin, le courant de breakdown des canaux et le délai de diffusion de spin. Validé par comparaison avec les résultats expérimentaux, ce modèle permet d'explorer les paramètres du dispositif liés à la fabrication, tels que les longueurs de canaux et les tailles de MTJ, et aide les concepteurs à éviter leur destruction. De plus, ce modèle, décrit avec Verilog-A sur Cadence et divisé en plusieurs blocs : injecteur, détecteur, canal et contact, permet une conception indépendante et une optimisation des circuits ASL qui facilitent la conception de circuits hiérarchiques et complexes. En outre, les expressions permettant le calcul de l'injection/accumulation de spin pour le dispositif ASL utilisé sont dérivées. Elles permettent de discuter des phénomènes expérimentaux observés sur les dispositifs ASL. Au niveau circuit, nous avons développé une méthodologie de conception de circuit/système, en tenant compte de la distribution des canaux, de l'interconnexion des portes et des différents rapports de courant d'injection provoqués par la diffusion de spin. Avec les spécifications et les contraintes du circuit/système, les fonctions booléennes du circuit sont synthétisées en fonction de la méthode de synthèse développée et des paramètres de niveau de fabrication : longueur des canaux, et tailles MTJ sont spécifiées. Basé sur cette méthodologie développée, les circuits combinatoires de base qui forment une bibliothèque de circuits sont conçus et évalués en utilisant le modèle compact développé. Au niveau du système, un circuit DCT, un circuit de convolution et un système Intel i7 sont évalués en explorant les problèmes d'interconnexion : la répartition de l'interconnexion entre les portes et le nombre de tampons inséré. Avec des paramètres théoriques, les résultats montrent que le circuit/système ASL peut surpasser le circuit/système basé sur CMOS. De plus, le pipeline du circuit basé sur ASL est discuté avec MTJ comme tampons insérés entre les étapes. La reconfigurabilité provoquée par les polarités/valeurs du courant d'injection et les états des terminaux de control des circuits ASL sont également discutés avec l'exploration reconfigurable des circuits logiques de base. / The CMOS technology has tremendously affected the development of the semi-conductor industry. However, as the technology node is scaled down, the CMOS technology faces significant challenges set by the leakage power and the short channel effects. To cope with this problem, researchers pay their attention to the spintronics in recent years, considering its possibilities to allow smaller size fabrication and lower power operations. The magnetic tunnel junction (MTJ) is one of the most important spintronic devices which can store binary data based on Tunnel MagnetoResistance (TMR) effect. Except for the non-volatile memory, MTJ can be also used to combine with or replace the CMOS circuits to implement a hybrid circuit, for the potential to achieve low power consumption and high speed performance. However, the problem of frequent spin-charge conversion in a hybrid circuit may cause large power consumption, which diminishes the advantage of the hybrid circuits. Therefore, the ASL concept which uses a pure spin current to transport the information is proposed for fewer charge-spin conversions, thus for less power consumption. The design of ASL device-based circuits leads to numerous challenges related to the heterogeneity they introduce and the large design space to explore. Hence, this thesis focus on filling the gap between application requirements at the system level and the device fabrication at the device level. In device level, we developed a compact model integrating the STT, the TMR, the spin injection/accumulation effects, the channel breakdown current and the spin diffusion delay. Validated by comparing with experimental results, this model allows exploring fabrication-related device parameters such as channel lengths and MTJ sizes and help designers to prevent from device damages. Moreover, programmed with Verilog-A on Cadence and divided into several blocks: injector, detector, channel and contact devices, this model allows the independent design and cross-layer optimization of ASL-based circuits, that eases the design of hierarchical, complex circuits. Furthermore, the spin injection/accumulation expressions for the used ASL device are derived, enabling to discuss the experimental phenomena of the ASL device. In circuit level, we developed a circuit/system design methodology, taking into account the channel distribution, the gate interconnection and the different injection current ratios caused by the spin diffusion. With circuit/system specifications and constraints, the boolean functions of a circuit are synthesized based on the developed synthesis method and fabrication-level parameters: channel lengths, MTJ sizes are specified. Based on this developed methodology, basic combinational circuits that form a circuit library are designed and evaluated by using the developed compact model. In system level, a DCT circuit, a convolution circuit and an Intel i7 system are evaluated exploring the interconnection issues: interconnection distribution between gates and inserted buffer count. With theoretical parameters, results show that ASL-based circuit/system can outperform CMOS-based circuit/system. Moreover, the pipelining schema of the ASL-based circuit is discussed with MTJ as latches inserted between stages. The reconfigurability caused by the injection current polarities/values and the control terminal states of ASL-based circuits are also discussed with the reconfigurable exploration of basic logic circuits.