Continuous process scale-down and emerging markets for low-power/low-voltage mobile systems call for low-voltage analog integrated circuits. Switched-capacitor circuits are the building blocks for analog signal processing and will encounter severe overdrive problems when operating at low-voltage conditions. There are several well-known techniques to bypass the problem. These approaches include: (1) The clock boosting schemes (e.g. 2VDD clock signal) which cannot be used in submicron low-voltage CMOS processes as gate oxide can only tolerate the technology's maximum voltage (VDD). (2) The use of scaled/lower threshold transistors, which are not always scalable to very low voltage supplies as it could suffer from an unacceptable amount of leakage current (e.g. the switch may not be fully turned off). (3) The use of bootstrapped clocking, which has added loading and possible reliability issues. (4) The switched-opamp (SO) technique which is fully compatible with low-voltage submicron CMOS processes but the operating speed limited due to slow transients from the opamp being switched off and on. In this thesis, the Opamp-Reset Switching Technique (ORST) topology is proposed for low-voltage operation. Instead of opamps being turned on and off as in the switched-opamp technique, the sourcing amplifier is placed in the unity-gain reset configuration to provide reset level at the output. In this way, high-speed operation is possible. The technique is applied to two ADCs as examples of low-voltage design. The first design is a 10-bit 25MSPS pipelined ADC using pseudo-differential structure. It is fabricated in a 0.35-��m CMOS process. It operates at 1.4V and consumes 21mW of total power. The second design is a two-stage algorithmic ADC with highly linear input sampling circuit. In addition to the low-voltage design techniques used in the pipelined ADC, radix-based digital calibration technique for multi-stage ADC is also proposed. The ADC uses a 0.18-��m CMOS technology. It operates at 0.9V supply with total power consumption of 9mW. Experimental results show that the proposed calibration technique reduces spurious free dynamic range from 47dB to 75dB and improves signal-to-noise and distortion ratio from 40dB to 55dB after calibration. / Graduation date: 2003

Graduation date: 1995

Thesis (Masters Diploma (Electrical Engineering)--Cape Technikon, Cape Town,1994 / This thesis describes the design, development and implementation of a digitising workstation for the electronics laboratory that utilises the personal computer.

Ko, Chi Tung. / On t.p. "delta" and "sigma" appear as the Greek letters. / Thesis submitted in: December 2007. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references. / Abstracts in English and Chinese. / Abstract --- p.1 / 摘要 --- p.3 / Acknowledgements --- p.4 / Table of Contents --- p.5 / List of Figures --- p.8 / List of Tables --- p.13 / Chapter Chapter 1 --- Introduction --- p.14 / Chapter 1.1 --- Motivation --- p.14 / Chapter 1.2 --- Objectives --- p.17 / Chapter 1.3 --- Organization of the Thesis --- p.17 / References --- p.18 / Chapter Chapter 2 --- Fundamentals of Delta-sigma Modulators --- p.20 / Chapter 2.1 --- Delta-sigma Modulator as a Feedback System --- p.20 / Chapter 2.2 --- Quantization Noise --- p.22 / Chapter 2.3 --- Oversampling --- p.23 / Chapter 2.4 --- Noise Shaping --- p.25 / Chapter 2.5 --- Performance Parameters --- p.27 / Chapter 2.6 --- Baseband Modulators vs Bandpass Modulators --- p.27 / Chapter 2.7 --- Discrete-time Modulators vs Continuous-time Modulators --- p.28 / Chapter 2.8 --- Single-bit Modulators vs Multi-bit Modulators --- p.29 / Chapter 2.9 --- Non-linearity and Image Problems in Multi-bit Delta-sigma Modulators --- p.29 / Chapter 2.9.1 --- Non-linearity Problem --- p.29 / Chapter 2.9.2 --- Image Problem --- p.31 / Reference --- p.36 / Chapter Chapter 3 --- Image Rejection and Non-linearity Suppression Techniques for Quadrature Multi-bit Δ¡♭ Modulators --- p.38 / Chapter 3.1 --- Quadrature DEM Technique --- p.38 / Chapter 3.1.1 --- Introduction and Working Principle --- p.38 / Chapter 3.1.2 --- Behavioral Simulation Results --- p.42 / Chapter 3.2 --- IQ DWA Technique --- p.44 / Chapter 3.2.1 --- Introduction and Working Principle --- p.44 / Chapter 3.2.2 --- Behavioral Simulation Results --- p.49 / Chapter 3.3 --- DWA and Bit-wise Data-Dependent DEM --- p.52 / Chapter 3.3.1 --- Introduction and Working Principle --- p.52 / Chapter 3.3.2 --- Behavioral Simulation Results --- p.54 / Chapter 3.4 --- Image Rejection Technique for Quadrature Mixer --- p.61 / Chapter 3.5 --- Conclusion --- p.63 / Reference --- p.64 / Chapter Chapter 4 --- System Design of a Multi-Bit CT Modulator for GSM/WCDMA Application --- p.65 / Chapter 4.1 --- Objective of Design and Design Specification --- p.65 / Chapter 4.2 --- Topology Selection --- p.65 / Chapter 4.3 --- Discrete-time Noise Transfer Function Generation --- p.66 / Chapter 4.4 --- Continuous-time Loop Filter Transfer Function Generation --- p.69 / Chapter 4.5 --- Behavioral Model of Modulator --- p.69 / Chapter 4.6 --- Dynamic Range Scaling --- p.75 / Chapter 4.7 --- Behavioral Modeling of Operational Amplifiers --- p.77 / Chapter 4.8 --- Impact of RC Variation on Performance --- p.85 / Chapter 4.9 --- Loop Filter Component Values --- p.88 / Chapter 4.10 --- Summary --- p.90 / Reference --- p.90 / Chapter Chapter 5 --- Transistor-level Implementation of Modulators --- p.92 / Chapter 5.1 --- Overview of Design --- p.92 / Chapter 5.2 --- Design of Operational Transconductance Amplifiers (OTAs) --- p.94 / Chapter 5.2.1 --- First Stage --- p.94 / Chapter 5.2.2 --- Second and Third Stages --- p.98 / Chapter 5.3 --- Design of Feed-forward Transconductance (Gm) Cells --- p.101 / Chapter 5.4 --- Design of Quantizer --- p.102 / Chapter 5.4.1 --- Reference Ladder Design --- p.102 / Chapter 5.4.2 --- Comparator Design --- p.104 / Chapter 5.5 --- Design of Feedback Digital-to-Analog Converter (DAC) --- p.106 / Chapter 5.5.1 --- DWA and DEM Logic --- p.107 / Chapter 5.5.2 --- DAC Circuit --- p.109 / Chapter 5.6 --- Design of Integrated Mixers --- p.111 / Chapter 5.7 --- Design of Clock Generators --- p.112 / Chapter 5.7.1 --- Master Clock Generator --- p.112 / Chapter 5.7.2 --- LO Clock Generator --- p.114 / Chapter 5.7.3 --- Simulation Results --- p.116 / Reference --- p.125 / Chapter Chapter 6 --- Physical Design of Modulators --- p.127 / Chapter 6.1 --- Floor Planning of Modulator --- p.127 / Chapter 6.2 --- Shielding of Sensitive Signals --- p.130 / Chapter 6.3 --- Common Centroid Layout --- p.130 / Chapter 6.4 --- Amplifier Layout --- p.132 / Reference --- p.137 / Chapter Chapter 7 --- Conclusions --- p.138 / Chapter 7.1 --- Conclusions --- p.138 / Chapter 7.2 --- Future Works --- p.138 / Appendix A Schematics of Building Blocks --- p.140 / First Stage Operational Amplifier --- p.140 / First Stage Amplifier Local Bias Circuit --- p.140 / Second and Third Stage Operational Amplifier --- p.141 / Second and Third Stage Local Bias Circuit --- p.141 / CMFB Circuit (First Stage) --- p.142 / CMFB Circuit (Second Stage) --- p.142 / Gm-Feed-forward Cells --- p.143 / Gm Feed-forward Cell Bias Circuit --- p.143 / Reference Ladder Circuit --- p.144 / Pre-amplifier Circuit --- p.145 / Latch Circuit --- p.145 / DAC Circuit (Unit Cell) --- p.146 / Author's Publications --- p.147

The thesis covers a series of PC programs that we have written that will enable users to easily design FIR linear phase lowpass digital filters and multistage sampling rate conversion systems. The first program is a rewrite of the McClellanParks computer program with some slight modifications. The second program uses an algorithm proposed by Rabiner that determines the length of a lowpass digital filter. Rabiner used a formula proposed by Herrmann et al. to initially estimate the filter length in his algorithm. The formula, however, assumes unity gain. We present a modification to the formula so that the gain of the filter is normalized to accommodate filters that have a gain greater than one (as in the case of a lowpass filter used in an interpolator). We have also changed the input specifications from digital to analog. Thus, the user supplies the sampling rate, passband frequency, stopband frequency, gain, and the respective maximum band errors. The program converts the specifications to digital. Then, the program iteratively estimates the filter length and interacts with the McClellan-Parks Program to determine the actual filter length that minimizes the maximum band errors. Once the actual length is known, the filter is designed and the filter coefficients may be saved to a file. Another new finding that we present is the condition that determines when to add a lowpass filter to a multistage decimator in order to reduce the total number of filter taps required to implement the system. In a typical example, we achieved a 34% reduction in the total required number of filter taps. The third program is a new program that optimizes the design of a multistage sampling rate conversion system based upon the sum of weighted computational rates and storage requirements. It determines the optimum number of stages and the corresponding upsampling and downsampling factors of each stage of the design. It also determines the length of the required lowpass digital filters using the second program. Quantization of the filter coefficients may have a significant impact on the frequency response. Consequently, we have included a routine within our program that determines the effects of such quantization on the allowable error margins within the passband and stopband. Once the filter coefficients are calculated, they can be saved to files and used in an appropriate implementation. The only requirements of the user are the initial sampling rate, final sampling rate, passband frequency, stopband frequency, corresponding maximum errors for each band, and the weighting factors to determine the optimization factor. We also present another new program that implements a sampling rate conversion from CD (44.1 kHz) to DAT (48 kHz) for digital audio. Using the third program to design the filter coefficients, the fourth program converts an input sequence (either samples of a sine wave or a unit sample sequence) sampled at the lower rate to an output sequence sampled at the higher rate. The frequency response is then plotted and the output block may be saved to a file.

The most accurate method for performing analog signal processing in MOS (metal-oxide-semiconductor) integrated circuits is through the use of switched-capacitor circuits. A switched-capacitor circuit operates as a discrete-time signal processor. These circuits have been used in a variety of applications, such as filters, gain stages, voltage-controlled oscillators, and modulators. A switched-capacitor circuit contains operational amplifiers (opamps), capacitators, switches, and a clock generator. Capacitors are used to define the state variables of a system. They store charges for a defined time interval, and determine the state variables as voltage differences. Switches are used to direct the flow of charges and to enable the charging and discharging of capacitors. Nonoverlapping clock signals control the switches and allow charge transfer between the capacitors. Opamps are used in order to perform high-accuracy charge transfer from one capacitor to another. The goal of this research is to design and explore future low-voltage switched-capacitor circuits, which are crucial for portable devices. Low-voltage operation is needed for two reasons: making reliable and accurate systems compatible with the submicron CMOS technology and reducing power consumption of the digital circuits. To this end, three different switched-capacitor integrators are proposed, which function with very low supply voltages. One of these configurations is used to design a lowpass ����� modulator for digital-audio applications. This modulator is fabricated and tested demonstrating 80 dB dynamic range with a 1-V supply voltage. The second part of this research is to show that these low-voltage circuits are suitable for modern wireless communication applications, where the clock and signal frequencies are very high. This part of the research has focused on bandpass analog-to-digital converters. Bandpass analog-to-digital converters are among the key components in wireless communication systems. They are used to digitize the received analog signal at an intermediate center frequency. Such converters are used for digital FM or AM radio applications and for portable communication devices, such as cellular phones. The main block, in these converters, is the resonator, which is tuned to a particular center frequency. A resonator must be designed such that it has a sharp peak at a specific center frequency. However, because of circuit imperfections, the resonant peak gain and/or the center frequency are degraded in existing architectures. Two novel switched-capacitor resonators were invented during the second part of this research. These resonators demonstrate superior performance as compared to previous architectures. A fourth-order low-voltage bandpass ����� modulator, using one of these resonators, has been designed. / Graduation date: 2002

Continuous-time (CT) Delta-Sigma Modulators (DSMs) have re-gained popularity recently for oversampling analog-to-digital conversion, because they are more suitable for low supply voltage implementation than their discrete-time (DT) counterparts, among other reasons. To the state of art at the low voltage front, a CT O.5-V audio-band DSM with a return-to-open feedback digital-to-analog converter has been reported. However, the O.5-V CT DSM has a limited performance of 74-dB SNDR due to clock jitters and other factors caused by the ultralow supply. / Finally, a O.5-V 2-1 cascaded CT DSM with SCR feedback is proposed. A new synthesis method is presented. Transistor-level simulations show that a 98dB SNDR is achieved over a 25-kHz signal bandwidth with a 6.4MHz sampling frequency and 350muW power consumption under a 0.5-V supply. / In this thesis, three novel ULV audio-band CT DSMs with high signal-to-noise-plus-distortion ratio (SNDR) are reported for a nominal supply of O.5V. The first one firstly realizes a switched-capacitor-resistor (SCR) feedback at O.5V, enabled by a fast amplifier at O.5V, for reduced clock jitter-sensitivity. Fabricated in a O.13mum CMOS process using only standard VT devices, the 3rd order modulator with distributed feedback occupies an active area of O.8mm2 . It achieves a measured SNDR of 81.2dB over a 25-kHz signal bandwidth while consuming 625muW at O.5-V. The measured modulator performance is consistent across a supply voltage range from O.5V to O.8V and a temperature range from -20°C to 90°C. Measurement results and thermal-noise calculation show that the peak SNDR is limited by thermal noise. / The scaling of the feature sizes of CMOS technologies results in a continuous reduction of supply voltage (VDD) to maintain reliability and to reduce the power dissipation per unit area for increasingly denser digital integrated circuits. The VDD for low-power digital circuits is predicted to drop to O.5V in about ten years. Ultra-low voltage (ULV) operation will also be required for the analog-to-digital converter, a universal functional block in mixed-signal integrated circuits, in situations where the benefits of using a single VDD out-weigh the overhead associated with multi-V DD solutions. / The second ULV CT DSM employs a feed-forward loop topology with SCR feedback. Designed in O.13mum CMOS process, the modulator achieves a post-layout simulation (thermal noise included) result of 89dB SNDR over a 25-kHz signal bandwidth. The 0.13mum CMOS chip consumes an active area of O.85mm2 and 682.5muW at O.5-V supply. It achieves an excellent measured performance of 87.8dB SNDR over a 25-kHz signal bandwidth and al02dB spurious-free dynamic range. To the best of our knowledge, this performance is the highest for DSMs in this supply voltage range. Thanks to the proposed adaptive biasing technique, the measured modulator performance is consistent across a supply voltage range from O.4V to O.75V and a temperature range from -20°C to 90°C. / Chen, Yan. / Adviser: Kong Pang Pun. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 127-135). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

The thesis covers a series of PC programs that we have written that will enable users to easily design FIR linear phase lowpass digital filters and multistage sampling rate conversion systems. The first program is a rewrite of the McClellanParks computer program with some slight modifications. The second program uses an algorithm proposed by Rabiner that determines the length of a lowpass digital filter. Rabiner used a formula proposed by Herrmann et al. to initially estimate the filter length in his algorithm. The formula, however, assumes unity gain. We present a modification to the formula so that the gain of the filter is normalized to accommodate filters that have a gain greater than one (as in the case of a lowpass filter used in an interpolator). We have also changed the input specifications from digital to analog. Thus, the user supplies the sampling rate, passband frequency, stopband frequency, gain, and the respective maximum band errors. The program converts the specifications to digital. Then, the program iteratively estimates the filter length and interacts with the McClellan-Parks Program to determine the actual filter length that minimizes the maximum band errors. Once the actual length is known, the filter is designed and the filter coefficients may be saved to a file. Another new finding that we present is the condition that determines when to add a lowpass filter to a multistage decimator in order to reduce the total number of filter taps required to implement the system. In a typical example, we achieved a 34% reduction in the total required number of filter taps. The third program is a new program that optimizes the design of a multistage sampling rate conversion system based upon the sum of weighted computational rates and storage requirements. It determines the optimum number of stages and the corresponding upsampling and downsampling factors of each stage of the design. It also determines the length of the required lowpass digital filters using the second program. Quantization of the filter coefficients may have a significant impact on the frequency response. Consequently, we have included a routine within our program that determines the effects of such quantization on the allowable error margins within the passband and stopband. Once the filter coefficients are calculated, they can be saved to files and used in an appropriate implementation. The only requirements of the user are the initial sampling rate, final sampling rate, passband frequency, stop band frequency, corresponding maximum errors for each band, and the weighting factors to determine the optimization factor. We also present another new program that implements a sampling rate conversion from CD (44.1 kHz) to DAT (48 kHz) for digital audio. Using the third program to design the filter coefficients, the fourth program converts an input sequence (either samples of a sine wave or a unit sample sequence) sampled at the lower rate to an output sequence sampled at the higher rate. The frequency response is then plotted and the output block may be saved to a file.

Graduation date: 1996

Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well- known for high accuracy applications since they benefit from noise shaping and they usually do not need highly accurate components. However, as a consequence of oversampling, they have limited signal bandwidth. The signal bandwidth (BW) of oversampled ADCs can be increased either by increasing the sampling rate or reducing the oversampling ratio (OSR). Reducing OSR is a more promising method for increasing the BW, since the sampling speed is usually limited by the technology. The advantageous properties (e.g. low in-band quantization, relaxed accuracy requirements of components) of oversampled ADCs are usually diminished at lower OSRs and preserving these properties requires complicated and power hungry architectures. In this thesis, different combinations of delta-sigma and pipelined ADCs are explored and new techniques for designing oversampled ADCs are proposed. A Hybrid Delta-Sigma/Pipelined (HDSP) ADC is presented. This ADC uses a pipelined ADC as the quantizer of a single-loop delta-sigma modulator and benefits from the aggressive quantization of the pipelined quantizer at low OSRs. A Noise-Shaped Pipelined ADC is proposed which exploits a delta-sigma modulator as the sub-ADC of a pipeline stage to reduce the sensitivity to the analog imperfection. Three prototype ADCs were fabricated in 0.18μm CMOS technology to verify the effectiveness of the proposed techniques. The performance of these architectures is among the best reported for high bandwidth oversampled ADCs. / Graduation date: 2011