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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Physical design with fabrication : friendly layout /

Wang, Jun, January 2004 (has links)
Thesis (Ph. D.)--University of Hong Kong, 2005.
2

Sensor-array chip hybrid for simultaneous multiple analyte detection /

Ranganathan, Lavakumar. January 2007 (has links)
Thesis (Ph.D.) OGI School of Science & Engineering at OHSU, October 2007. / Includes bibliographical references (leaves 149-152).
3

A VHDL description of speech recognition front-end

Xiao, Xin 17 May 2001 (has links)
This thesis investigates an implementation of speech recognition front-end. It is an application specific integrated circuit (ASIC) solution. A Mel Cepstrum algorithm is implemented for the feature extraction. We present a new mixed split-radix and radix-2 Fast Fourier Transform (FFT) algorithm, which can effectively minimize the number of complex multiplications in the speech recognition front-end. A prime length discrete cosine transform (DCT) is done effectively through the use of two shorter length correlations. The algorithm results in a circular correlation structure that is suitable for a constant coefficient multiplication and shift-register realization. The multiplicative normalization algorithm is used for square root function. Radix-2 algorithm is used in the first 5 stages and radix-4 algorithm is used in the other stages to speed up the convergence. A similar normalization algorithm is present for natural logarithm. / Graduation date: 2002
4

Reuse and estimation techniques for embedded systems-on-a-chip /

Peixoto, Helvio Pereira, January 1999 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 116-121). Available also in a digital version from Dissertation Abstracts.
5

Physical design with fabrication: friendly layout

Wang, Jun, 王雋 January 2004 (has links)
published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy
6

Design synthesis of application-specification ICs for DSP

Ben Romdhane Mohamed Salah 12 1900 (has links)
No description available.
7

A formal approach to hardware design /

Staunstrup, Jørgen. January 1994 (has links)
Techn. Univ., Diss.--Lungby, 1994.
8

Digital implementation of high speed pulse shaping filters and address based serial peripheral interface design

Rachamadugu, Arun. January 2008 (has links)
Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Laskar, Joy; Committee Member: Anderson, David; Committee Member: Cressler, John. Part of the SMARTech Electronic Thesis and Dissertation Collection.
9

Analog ASICs for a Depth of Interaction (DOI) Positron Emission Tomography (PET) dectector module /

Yu, Haiming. January 1999 (has links)
Thesis (Ph. D.)--University of Washington, 1999. / Vita. Includes bibliographical references (leaves 126-140).
10

Architecture and design flow for a highly efficient structured ASIC. / 一種高效結構化專用集成電路的體系結構和設計流程 / Yi zhong gao xiao jie gou hua zhuan yong ji cheng dian lu de ti xi jie gou he she ji liu cheng

January 2011 (has links)
Ho, Man Ho. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (p. 60-64). / Abstracts in English and Chinese. / Abstract --- p.i / Chinese Abstract --- p.iii / Acknowledgement --- p.v / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Objectives --- p.3 / Chapter 1.3 --- Contributions --- p.4 / Chapter 1.4 --- Thesis Organization --- p.5 / Chapter 2 --- Background Study --- p.6 / Chapter 2.1 --- Introduction --- p.6 / Chapter 2.2 --- Architecture & Design Flows --- p.6 / Chapter 2.3 --- Summary --- p.11 / Chapter 3 --- Architecture --- p.14 / Chapter 3.1 --- Overview --- p.14 / Chapter 3.2 --- Fabric Architecture --- p.15 / Chapter 3.2.1 --- Programmable Layers --- p.15 / Chapter 3.2.2 --- Fabric Organization --- p.16 / Chapter 3.3 --- Logic Block Designs --- p.19 / Chapter 3.3.1 --- Lookup-table (LUT) Based Logic Block --- p.19 / Chapter 3.3.2 --- Static CMOS Style Logic Block --- p.22 / Chapter 3.4 --- Summary --- p.26 / Chapter 4 --- EDA Design Flow --- p.27 / Chapter 4.1 --- Overview --- p.27 / Chapter 4.2 --- Library Preparation --- p.27 / Chapter 4.3 --- Design Synthesis --- p.29 / Chapter 4.4 --- Fabric Creation & Design Mapping Flows --- p.30 / Chapter 4.5 --- Summary --- p.35 / Chapter 5 --- Experimental Results --- p.36 / Chapter 5.1 --- Benchmark Circuits Description --- p.36 / Chapter 5.2 --- Experiment Configurations --- p.37 / Chapter 5.2.1 --- Synthesis --- p.38 / Chapter 5.2.2 --- Placement & Routing --- p.39 / Chapter 5.3 --- Comparison Metrics --- p.40 / Chapter 5.4 --- Area & Critical Path Delay Comparisons --- p.41 / Chapter 5.5 --- Summary --- p.46 / Chapter 6 --- Prototypes Testing --- p.47 / Chapter 6.1 --- Overview --- p.47 / Chapter 6.2 --- Second Tape-out --- p.47 / Chapter 6.2.1 --- Sample Application --- p.48 / Chapter 6.2.2 --- Signoff preparations --- p.50 / Chapter 6.2.3 --- Results for Test unit --- p.51 / Chapter 6.2.4 --- Functional test of Peak unit --- p.52 / Chapter 6.3 --- Third Tape-out --- p.53 / Chapter 6.3.1 --- Test Results . --- p.54 / Chapter 7 --- Conclusion --- p.57 / Chapter 7.1 --- Future Works --- p.58 / Bibliography --- p.59

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