Report (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 60-62). Also available via the Internet.

The effectiveness of implementing field programmable gate arrays (FPGAs) in communication, military, space and high radiation environment applications, coupled with the increased accessibility of private individuals and researchers to launch satellites, has led to an increased interest in commercial off the shelf components. The metal oxide semiconductor (MOS) structures of FPGAs however, are sensitive to radiation effects which can lead to decreased reliability of the device. In order to successfully implement a FPGA based system in a radiation environment, such as on-board a satellite, the single event upset (SEU) and total ionizing dose (TID) characteristics of the device must first be established. This research experimentally determines a research procedure which could accurately determine the SEU cross sections and TID characteristics of various mitigation techniques as well as control circuits implemented in a ProASIC3 A3P1000 FPGA. To gain an understanding of the SEU effects of the implemented circuits, the test FPGA was irradiated by a 66MeV proton beam at the iTemba LABS facility. Through means of irradiation, the SEU cross section of various communication, motor control and mitigation schemes circuits, induced by high energy proton strikes was investigated. The implementation of a full global triple modular redundancy (TMR) and a combination of TMR and a AND-OR multiplexer filter was found to most effectively mitigate SEUs in comparison to the other techniques. When comparing the communication and motor control circuits, the high frequency I2C and SPI circuits experienced a higher number of upsets when compared to a low frequency servo motor control circuit. To gain a better understanding of the absorbed dose effects, experimental TID testing was conducted by irradiating the test FPGA with a cobalt-60 (Co-60) source. An accumulated absorbed dose resulted in the fluctuation of the device supply current and operating voltages as well as resulted in output errors. The TMR and TMR filtering combination mitigation techniques again were found to be the most effective methods of mitigation.

Accurate predict of ASIC power diss ion is possible using VHDL. By using physical data types, timing and power estimations can be based on estimated typical fan-in and fan-out conditions and a pre-characterized circuit library. Actual load conditions can be back annotated to yield actual power dissipation. Methods to determine pattern sensitive and pattern insensitive power diss ion are presented. This approach uses the concept of load ports VHDL to permit self determining load conditions based on historical wiring data for a given technology. <p>Modeling techniques for VHDL circuit descriptions are developed that allow propagation delay, output rise and fall time, power dissipation be determined from VHDL event simulation. An example of an ALU such as the 74LS181 is presented. / Master of Science

Among the many efforts to improve the IC test process are tests that attempt to differentiate between healthy and defective or low reliability ICs by manipulating the operating conditions of the IC being tested. This thesis attempts to improve the common understanding of multiple and targeted temperature testing by evaluating work published on the subject to date and by presenting previously unpublished empirical observations. The empirical observations are made from SCAN and LBIST based MinVDD measurements, Static IDD measurements, as well as parametric measurements of transistor characteristics. The test vehicles used are 0.25μm and 0.18μm CMOS ASICs fabricated by LSI Logic. An IC’s performance is bound by a three dimensional space defined by VDD, frequency, and temperature. A model is presented to explain the boundaries of the performance region in terms of the ability of the IC’s constituent transistors to provide power and the Zero-Temperature-Coefficient (ZTC). Also, it is determined that multiple temperature testing can add new tests to current test suites to improve the resolution between healthy and defective ICs.

No description available.

A method to implement high-speed pulse shaping filters has been discussed. This technique uses a unique look up table based architecture implemented in 90nm CMOS using a standard cell based ASIC flow. This method enables the implementation of pulse shaping filters for multi-giga bit per second data transmission. In this work a raised cosine FIR filter operating at 4 GHz has been designed. Various Implementation issues and solutions encountered during the synthesis and layout stages have been discussed. In the second portion of this work, the design of a unique address based serial peripheral interface (SPI) for initializing, calibrating and controlling various blocks in a large system has been discussed. Some modifications have been made to the standard four-wire SPI protocol to enable high control speeds with lesser number of top-level pads. This interface has been designed to function in the duplex mode to do both read and write operations.

Thesis (M.S.E.C.E.)--Baylor University, 2008. / Includes bibliographical references (p. 322-323)

Thesis (Ph.D.). / Written for the Dept. of Electrical and Computer Engineering. Title from title page of PDF (viewed 2009/06/08). Includes bibliographical references.

Thesis (Ph. D.)--University of Washington, 1999. / Vita. Includes bibliographical references (p. 189-193).

Thesis (M.S.)--Rochester Institute of Technology, 2008. / Typescript. Includes bibliographical references (leaves 59-60).