"Elliptic Curve Cryptosystems (ECCs) are utilized as an alternative to traditional public-key cryptosystems, and are more suitable for resource limited environments due to smaller parameter size. In this dissertation we carry out a thorough investigation of side-channel attack aware ECC implementations over finite fields of prime characteristic including the recently introduced Edwards formulation of elliptic curves, which have built-in resiliency against simple side-channel attacks. We implement Joye's highly regular add-always scalar multiplication algorithm both with the Weierstrass and Edwards formulation of elliptic curves. We also propose a technique to apply non-adjacent form (NAF) scalar multiplication algorithm with side-channel security using the Edwards formulation. Our results show that the Edwards formulation allows increased area-time performance with projective coordinates. However, the Weierstrass formulation with affine coordinates results in the simplest architecture, and therefore has the best area-time performance as long as an efficient modular divider is available."

The efficient high-throughput VLSI implementation of near-optimal multiple-input multiple-output (MIMO) detectors for 4x4 MIMO systems in high-order quadrature amplitude modulation (QAM) schemes has been a major challenge in the literature. To address this challenge, this thesis introduces a novel scalable pipelined VLSI architecture for a 4x4 64-QAM MIMO receiver based on K-Best lattice decoders. The key contribution is a means of expanding/visiting the intermediate nodes of the search tree on-demand, rather than exhaustively along with three types of distributed sorters operating in a pipelined structure. The combined expansion and sorting cores are able to find the K best candidates in K clock cycles. The proposed architecture has a fixed critical path independent of the constellation order, on-demand expansion scheme, efficient distributed sorters, and is scalable to a higher number of antennas/constellation orders. Fabricated in 0.13um CMOS, it operates at a significantly higher throughput (5.8x better) than currently reported schemes and occupies 0.95 mm2 core area. Operating at 282 MHz clock frequency, it dissipates 135 mW at 1.3 V supply with no performance loss. It achieves an SNR-independent decoding throughput of 675 Mbps satisfying the requirements of IEEE 802.16m and Long Term Evolution (LTE) systems. The measurements confirm that this design consumes 3.0x less energy/bit compared to the previous best design.

The efficient high-throughput VLSI implementation of near-optimal multiple-input multiple-output (MIMO) detectors for 4x4 MIMO systems in high-order quadrature amplitude modulation (QAM) schemes has been a major challenge in the literature. To address this challenge, this thesis introduces a novel scalable pipelined VLSI architecture for a 4x4 64-QAM MIMO receiver based on K-Best lattice decoders. The key contribution is a means of expanding/visiting the intermediate nodes of the search tree on-demand, rather than exhaustively along with three types of distributed sorters operating in a pipelined structure. The combined expansion and sorting cores are able to find the K best candidates in K clock cycles. The proposed architecture has a fixed critical path independent of the constellation order, on-demand expansion scheme, efficient distributed sorters, and is scalable to a higher number of antennas/constellation orders. Fabricated in 0.13um CMOS, it operates at a significantly higher throughput (5.8x better) than currently reported schemes and occupies 0.95 mm2 core area. Operating at 282 MHz clock frequency, it dissipates 135 mW at 1.3 V supply with no performance loss. It achieves an SNR-independent decoding throughput of 675 Mbps satisfying the requirements of IEEE 802.16m and Long Term Evolution (LTE) systems. The measurements confirm that this design consumes 3.0x less energy/bit compared to the previous best design.

A method to implement high-speed pulse shaping filters has been discussed. This technique uses a unique look up table based architecture implemented in 90nm CMOS using a standard cell based ASIC flow. This method enables the implementation of pulse shaping filters for multi-giga bit per second data transmission. In this work a raised cosine FIR filter operating at 4 GHz has been designed. Various Implementation issues and solutions encountered during the synthesis and layout stages have been discussed. In the second portion of this work, the design of a unique address based serial peripheral interface (SPI) for initializing, calibrating and controlling various blocks in a large system has been discussed. Some modifications have been made to the standard four-wire SPI protocol to enable high control speeds with lesser number of top-level pads. This interface has been designed to function in the duplex mode to do both read and write operations.

Les applications dans le domaine des communications numériques deviennent de plus en plus complexes et diversifiées. En témoigne la nécessité de corriger les erreurs des messages transmis. Pour répondre à cette problématique, des codes correcteurs d’erreurs sont utilisés. En particulier, les Codes Polaires qui font l’objet de cette thèse. Ils ont été découverts récemment (2008) par Arıkan. Ils sont considérés comme une découverte importante dans le domaine des codes correcteurs d’erreurs. Leur aspect pratique va de paire avec la capacité à proposer une implémentation matérielle de décodeur. Le sujet de cette thèse porte sur l’exploration architecturale de décodeurs de Codes Polaires implémentant des algorithmes de décodage particuliers. Ainsi, le sujet gravite autour de deux algorithmes de décodage : un premier algorithme de décodage à décisions dures et un autre algorithme de décodage à décisions souples.Le premier algorithme de décodage, à décisions dures, traité dans cette thèse repose sur l’algorithme par annulation successive (SC) comme proposé originellement. L’analyse des implémentations de décodeurs montre que l’unité de calcul des sommes partielles est complexe. De plus,la quantité mémoire ressort de cette analyse comme étant un point limitant de l’implémentation de décodeurs de taille importante. Les recherches menées afin de palier ces problèmes montrent qu’une architecture de mise à jour des sommes partielles à base de registres à décalages permet de réduire la complexité de cette unité. Nous avons également proposé une nouvelle méthodologie permettant de revoir la conception d’une architecture de décodeur déjà existante de manière relativement simple afin de réduire le besoin en mémoire. Des synthèses en technologie ASIC et sur cibles FPGA ont été effectués pour caractériser ces contributions. Le second algorithme de décodage, à décisions souples, traité dans ce mémoire, est l’algorithme SCAN. L’étude de l’état de l’art montre que le seul autre algorithme à décisions souples implémenté est l’algorithme BP. Cependant, il nécessite une cinquantaine d’itérations pour obtenir des performances de décodages au niveau de l’algorithme SC. De plus, son besoin mémoire le rend non implémentable pour des tailles de codes élevées. L’intérêt de l’algorithme SCAN réside dans ses performances qui sont meilleures que celles de l’algorithme BP avec seulement 2 itérations.De plus, sa plus faible empreinte mémoire le rend plus pratique et permet l’implémentation de décodeurs plus grands. Nous proposons dans cette thèse une première implémentation de cetalgorithme sur cibles FPGA. Des synthèses sur cibles FPGA ont été effectuées pour pouvoir comparer le décodeur SCAN avec les décodeurs BP de l’état de l’art.Les contributions proposées dans cette thèse ont permis d’apporter une réduction de la complexité matérielle du calcul des sommes partielles ainsi que du besoin général du décodeur en éléments de mémorisation. Le décodeur SCAN peut être utilisé dans la chaîne de communication avec d’autres blocs nécessitant des entrées souples. Cela permet alors d’ouvrir le champ d’applications des Codes Polaires à ces blocs. / Applications in the field of digital communications are becoming increasingly complex and diversified. Hence, the need to correct the transmitted message mistakes becomes an issue to be dealt with. To address this problem, error correcting codes are used. In particular, Polar Codes that are the subject of this thesis. They have recently been discovered (2008) by Arikan. They are considered an important discovery in the field of error correcting codes. Their practicality goes hand in hand with the ability to propose a hardware implementation of a decoder. The subject of this thesis focuses on the architectural exploration of Polar Code decoders implementing particular decoding algorithms. Thus, the subject revolves around two decoding algorithms: a first decoding algorithm, returning hard decisions, and another decoding algorithm, returning soft decisions.The first decoding algorithm, treated in this thesis, is based on the hard decision algorithm called "successive cancellation" (SC) as originally proposed. Analysis of implementations of SC decoders shows that the partial sum computation unit is complex. Moreover, the memory amount from this analysis limits the implementation of large decoders. Research conducted in order to solve these problems presents an original architecture, based on shift registers, to compute the partial sums. This architecture allows to reduce the complexity and increase the maximum working frequency of this unit. We also proposed a new methodology to redesign an existing decoder architecture, relatively simply, to reduce memory requirements. ASIC and FPGA syntheses were performed to characterize these contributions.The second decoding algorithm treated in this thesis is the soft decision algorithm called SCAN. The study of the state of the art shows that the only other implemented soft decision algorithm is the BP algorithm. However, it requires about fifty iterations to obtain the decoding performances of the SC algorithm. In addition, its memory requirements make it not implementable for huge code sizes. The interest of the SCAN algorithm lies in its performances which are better than those of the BP algorithm with only two iterations. In addition, its lower memory footprint makes it more convenient and allows the implementation of larger decoders. We propose in this thesis a first implementation of this algorithm on FPGA targets. FPGA syntheses were carried out in order to compare the SCAN decoder with BP decoders in the state of the art.The contributions proposed in this thesis allowed to bring a complexity reduction of the partial sum computation unit. Moreover, the amount of memory required by an SC decoder has been decreased. At last, a SCAN decoder has been proposed and can be used in the communication field with other blocks requiring soft inputs. This then broadens the application field of Polar Codes.