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CONVOLUTIONAL CODING FOR HR RADIO TELEMETRY SYSTEMXianming, Zhao, Tingxian, Zhou, Honglin, Zhao, Qun, Lu 11 1900 (has links)
International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / This paper discusses an error-correcting scheme applied to a telemetry system over
HF radio channel. According to the statistical properties of transmission error on HF
radio channel, the scheme uses one important diffuse convolutional code, which is
threshold decoded and corrects the random or burst errors. The operation of this code
is explained, and a new method for word synchronization and bit synchronization is
proposed. Coding and decoding, word synchronization, and bit synchronization are all
activated by software program so as to greatly improve the flexibleness and
applicability of the data transmission system. Test results of error-correcting are given
for a variety of bit-error-rate (BER)s on HF radio channel.
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A New Error Control Scheme for Remote Control SystemZhou, Tingxian, Yin, Xiaohua, Zhao, Xianming 10 1900 (has links)
International Telemetering Conference Proceedings / October 17-20, 1994 / Town & Country Hotel and Conference Center, San Diego, California / How to rise the reliability of the data transmission is one of the main problem faced by modern digital communication designers. This paper studies the error-correcting codes being suitable for the channel existing both the random and burst error. A new error control scheme is given. The scheme is a concatenated coding system using an interleaved Reed-Solomon code with symbols over GF (24) as the outer code and a Viterbi-decoded convolutional code as the inner code. As a result of the computer simulation, it is proved that the concatenated coding system has a output at a very low bit error rate (BER)and can correct a lot of compound error patterns. It is suitable for the serious disturb channel existing both the random and burst error. This scheme will be adopted for a remote control system.
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Utilizing Correct Prior Probability Calculation to Improve Performance of Low-Density Parity-Check Codes in the Presence of Burst NoiseNeal, David A. 01 May 2012 (has links)
Low-density parity-check (LDPC) codes provide excellent error correction performance and can approach the channel capacity, but their performance degrades significantly in the presence of burst noise. Bursts of errors occur in many common channels, including the magnetic recording and the wireless communications channels. Strategies such as interleaving have been developed to help compensate for bursts errors. These techniques do not exploit the correlations that can exist between the noise variance on observations in and out of the bursts. These differences can be exploited in calculations of prior probabilities to improve accuracy of soft information that is sent to the LDPC decoder.
Effects of using different noise variances in the calculation of prior probabilities are investigated. Using the true variance of each observation improves performance. A novel burst detector utilizing the forward/backward algorithm is developed to determine the state of each observation, allowing the correct variance to be selected for each. Comparisons between this approach and existing techniques demonstrate improved performance. The approach is generalized and potential future research is discussed.
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A 1Mbps 0.18μm CMOS Soft-output Decoder for Product Turbo CodesBade, Peter 30 July 2009 (has links)
A product turbo code (PTC) decoder application specific integrated circuit (ASIC) is designed in 0.18μm 1P6M CMOS with embedded SRAM. From simulation, an operating frequency of 73.1 MHz at typical conditions is obtained, yielding a throughput of 3.8 Mbps with 4 decoding iterations, while consuming 103.4 mW. The total area is 5.13 mm2. Assuming the ASIC would be used as a hard macro, the area could be reduced to 1.7 mm2. The ASIC was tested at 20 MHz under typical conditions, which resulted in a throughput of 1.0 Mbps at 1.8V supply while consuming 36.6 mW.
By making a slight modification, this design can be easily scaled to support IEEE 802.16d WiMAX. Allow for this, and moving to a 45nm process an estimated throughput of 9.44 Mbps with 4 iterations can be obtained. Total macro area would be approximately 0.11 mm2.
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A 1Mbps 0.18μm CMOS Soft-output Decoder for Product Turbo CodesBade, Peter 30 July 2009 (has links)
A product turbo code (PTC) decoder application specific integrated circuit (ASIC) is designed in 0.18μm 1P6M CMOS with embedded SRAM. From simulation, an operating frequency of 73.1 MHz at typical conditions is obtained, yielding a throughput of 3.8 Mbps with 4 decoding iterations, while consuming 103.4 mW. The total area is 5.13 mm2. Assuming the ASIC would be used as a hard macro, the area could be reduced to 1.7 mm2. The ASIC was tested at 20 MHz under typical conditions, which resulted in a throughput of 1.0 Mbps at 1.8V supply while consuming 36.6 mW.
By making a slight modification, this design can be easily scaled to support IEEE 802.16d WiMAX. Allow for this, and moving to a 45nm process an estimated throughput of 9.44 Mbps with 4 iterations can be obtained. Total macro area would be approximately 0.11 mm2.
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Expanderové kódy / Expander codesMachová, Markéta January 2021 (has links)
Error-corecting codes are used during most of data transmissions these days. To save space, we would like to use codes which are able to correct enough errors without extending the message too much. The expander codes look promising - they are asymptotically optimal, however, in practice they are just too long. Better expander constructions could be achieved via randomness con- ductors. In this thesis, we explain what conductors are and which constructions are possible for them. In the end we will convert them to expanders and almost get expander codes which are short enough for practical use but nevertheless good. 1
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Etudes de récepteurs MIMO-LDPC itératifs / LDPC coded MIMO iterative receiversCharaf, Akl 04 April 2012 (has links)
L’objectif de cette thèse est l’étude de récepteurs MIMO LDPC itératifs. Les techniques MIMO permettent d’augmenter la capacité des réseaux sans fil sans la nécessité de ressources fréquentielles additives. Associées aux schémas de modulations multiporteuses CP-OFDM, les techniques MIMO sont ainsi devenues la pierre angulaire pour les systèmes sans fil à haute efficacité spectrale. La réception optimale peut être obtenue à l’aide d’une réception conjointe (Egalisation/Décodage). Étant très complexe, la réception conjointe n’est pas envisagée et l’égalisation et le décodage sont réalisés disjointement au coût d’une dégradation significative en performances. Entre ces deux solutions, la réception itérative trouve son intérêt pour sa capacité à s’approcher des performances optimales avec une complexité réduite. La conception de récepteurs itératifs pour certaines applications, de type WiFi à titre d’exemple doit respecter la structure du code imposée par la norme. Ces codes ne sont pas optimisés pour des récepteurs itératifs. En observant l’effet du nombre d' itérations dans le processus itératif, on montre par simulation que l’ordonnancement des itérations décodage LDPC/Turbo-égalisation joue un rôle important dans la complexité et le délai du récepteur. Nous proposons de définir des ordonnancements permettant de réduire la complexité globale du récepteur. Deux approches sont proposées, une approche statique ainsi qu'une autre dynamique. Ensuite nous considérons un système multi-utilisateur avec un accès multiple par répartition spatiale. Nous étudions l’intérêt de la réception itérative dans ce contexte tenant en compte la différence de puissance signale utile/interférence. / The aim of this thesis is to address the design of iterative MIMO receivers using LDPC Error Correcting codes. MIMO techniques enable capacity increase in wireless networks with no additional frequency ressources. The associationof MIMO with multicarrier modulation techniques OFDM made them the cornerstone of emerging high rate wireless networks. Optimal reception can be achieved using joint detection and decoding at the expense of a huge complexity making it impractical. Disjoint reception is then the most used. The design of iterative receivers for some applications using LDPC codes like Wifi (IEEE 802.11n) is constrained by the standard code structure which is not optimized for such kind of receivers. By observing the effect of the number of iterations on performance and complexity we underline the interest of scheduling LDPC decoding iterations and turboequalization iterations. We propose to define schedules for the iterative receiver in order to reduce its complexity while preserving its performance. Two approaches are used : static and dynamic scheduling. The second part of this work is concerns Multiuser MIMO using Spatial Division Multiple Access. We explore and evaluate the interest of using iterative reception to cancel residual inter-user interference.
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An Area-Efficient Architecture for the Implementation of LDPC DecoderYang, Lan 25 April 2011 (has links)
No description available.
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Device Specific Key Generation Technique for Anti-Counterfeiting Methods Using FPGA Based Physically Unclonable Functions and Artificial IntelligencePappala, Swetha 27 September 2012 (has links)
No description available.
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Contribuições aos metodos de procura dos codigos de treliça otimos sobre novas partições de reticulados / Contributions to the search methods of optimum trellis codes on new lattices partitioningSilva Filho, João Coelho 12 December 2008 (has links)
Orientadores: Walter da Cunha Borelli, Emilia de Mendonça Rosa Marques / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-13T08:38:40Z (GMT). No. of bitstreams: 1
SilvaFilho_JoaoCoelho_D.pdf: 842540 bytes, checksum: 07a4f12e39ce13ce6c183f2983fbe70f (MD5)
Previous issue date: 2008 / Resumo: Esta tese apresenta contribuições aos esquemas de modulação codificada para os códigos de treliça sobre partições de reticulados. Uma das principais contribuições é a construção dos códigos de treliça sobre novas partições de reticulados e também em cadeias de partições. Para otimizar a procura dos códigos de treliça ótimos, é construído um algoritmo de procura. É proposta uma classe de equivalência utilizada para excluir as matrizes geradoras de códigos equivalentes, sendo que esta classe de equivalência quando aplicada ao algoritmo de procura dos códigos de treliça ótimos diminui a quantidade de matrizes geradoras a ser investigada. Apresentam-se, vários exemplos de códigos de treliça sobre reticulados quociente nos espaços bi-dimensional, tridimensional e tetra-dimensional com satisfatórios ganhos de codificação e menor energia média das constelações de sinais. / Abstract: This thesis presents some contributions to the coded modulation schemes for the trellis codes based on lattices partitioning. One of the main contributions is the construction of the trellis codes based on novel lattices partitioning and also on chains partitioning. In order to optimize the search for the optimum trellis codes, a search algorithm was proposed. An equivalence class is proposed to exclude the generator matrix of equivalent codes. This equivalence class, when applied to the search algorithm for optimum trellis codes, reduces quite strongly the number of generator matrices to be investigated. Several examples of trellis codes on lattices quotient are shown in bi-dimensional, three-dimensional and tetra-dimensional spaces with satisfactory coding gain and lower average energy of the signal constellations. / Doutorado / Telecomunicações e Telemática / Doutor em Engenharia Elétrica
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