In state-of-the-art fiber-optics communication systems the fixed forward error correction (FEC) and constellation size are employed. While it is important to closely approach the Shannon limit by using turbo product codes (TPC) and low-density parity-check (LDPC) codes with soft-decision decoding (SDD) algorithm; rate-adaptive techniques, which enable increased information rates over short links and reliable transmission over long links, are likely to become more important with ever-increasing network traffic demands. In this invited paper, we describe a rate adaptive non-binary LDPC coding technique, and demonstrate its flexibility and good performance exhibiting no error floor at BER down to 10(-15) in entire code rate range, by FPGA-based emulation, making it a viable solution in the next-generation high-speed intelligent aggregation networks.

<p>As the complexity of Very Large Scale Integration (VLSI) circuits dramatically increases by improvements of technology, there is a huge interests to shift different applications from analog to digital domain. While there are many platform available for this shift, Field Programmable Gate Arrays (FPGAs) hold an attractive position because of their performance, power consumption and configurability. Comparing with Application Specific Integrated Circuit (ASIC) and Digital Signal Processor (DSP), FPGA stands in the middle. It is easier to implement a function on FPGA than ASIC which is to perform a fixed operation. Although, DSP can implement versatile functions, its computational power is not high enough to support the high data rate of FPGA.</p><p>This report is the outcome and result of a master thesis at University of Linköping, Sweden. This report tries to cover both theoretical and hardware aspects of implementation of a Farrow structure for sample rate conversion on FPGA.</p><p>The intention of this work was to contribute to what is nowadays the main focus of communication engineers: designing flexible radio systems. Flexible radio systems are interactive and dynamic by definition. That is why a low-cost, flexible multimode terminal is crucially important to support different telecommunication standards and scenarios. In this thesis, FPGA implementation of complete Farrow system is presented. Matlab/Simulink, and VHDL are used in this thesis work as the prime software.</p>

As the complexity of Very Large Scale Integration (VLSI) circuits dramatically increases by improvements of technology, there is a huge interests to shift different applications from analog to digital domain. While there are many platform available for this shift, Field Programmable Gate Arrays (FPGAs) hold an attractive position because of their performance, power consumption and configurability. Comparing with Application Specific Integrated Circuit (ASIC) and Digital Signal Processor (DSP), FPGA stands in the middle. It is easier to implement a function on FPGA than ASIC which is to perform a fixed operation. Although, DSP can implement versatile functions, its computational power is not high enough to support the high data rate of FPGA. This report is the outcome and result of a master thesis at University of Linköping, Sweden. This report tries to cover both theoretical and hardware aspects of implementation of a Farrow structure for sample rate conversion on FPGA. The intention of this work was to contribute to what is nowadays the main focus of communication engineers: designing flexible radio systems. Flexible radio systems are interactive and dynamic by definition. That is why a low-cost, flexible multimode terminal is crucially important to support different telecommunication standards and scenarios. In this thesis, FPGA implementation of complete Farrow system is presented. Matlab/Simulink, and VHDL are used in this thesis work as the prime software.

<p> </p><p>Modern nuclear and particle physics experiments run at a very high reaction rate and are able to deliver a data rate of up to hundred GBytes/s.  This data rate is far beyond the storage and on-line analysis capability. Fortunately physicists have only interest in a very small proportion among the huge amounts of data. Therefore in order to select the interesting data and reject the background by sophisticated pattern recognition processing, it is essential to realize an efficient data acquisition and trigger system which results in a reduced data rate by several orders of magnitude. Motivated by the requirements from multiple experiment applications, we are developing a high-end reconfigurable computation platform for data acquisition and triggering. The system consists of a scalable number of compute nodes, which are fully interconnected by high-speed communication channels. Each compute node features 5 Xilinx Virtex-4 FX60 FPGAs and up to 10 GBytesDDR2 memory. A hardware/software co-design approach is proposed to develop custom applications on the platform, partitioning performance-critical calculation to the FPGA hardware fabric while leaving flexible and slow controls to the embedded CPU plus the operating system. The system is expected to be high-performance and general-purpose for various applications especially in the physics experiment domain.</p><p>As a case study, the particle track reconstruction algorithm for HADES has been developed and implemented on the computation platform in the format of processing engines. The Tracking Processing Unit (TPU) recognizes peak bins on the projection plane and reconstructs particle tracks in realtime. Implementation results demonstrate its acceptable resource utilization and the feasibility to implement the module together with the sys-tem design on the FPGA. Experimental results show that the online track reconstruction computation achieves 10.8 - 24.3 times performance acceleration per TPU module when compared to the software solution on a Xeon2.4 GHz commodity server.</p>

No description available.

Tato práce je zaměřena na zpracování a analýzu USB komunikačního protokolu a implementace jeho jednotlivých částí do FPGA obvodu s využitím programovacího jazyka VHDL. Ve finální podobě by měla práce představovat souhrnný a ucelený dokument popisující principy USB rozhraní a jeho komunikace doplněných praktickým návrhem v jazyce VHDL, který by byl schopen převést data do USB.

Unmanned vehicles (UVs) are seeing more widespread use in military, scientific, and civil sectors in recent years. These UVs range from unmanned air and ground vehicles to surface and underwater vehicles. Each of these different UVs has its own inherent strengths and weaknesses, from payload to freedom of movement. Research in this field is growing primarily because of the National Defense Act of 2001 mandating that one-third of all military vehicles be unmanned by 2015. Research using small UVs, in particular, is a growing because small UVs can go places that may be too dangerous for humans. Because of the limitations inherent in small UVs, including power consumption and payload, the selection of light weight and low power sensors and processors becomes critical. Low power CMOS cameras and real-time vision processing algorithms can provide fast and reliable information to the UVs. These vision algorithms often require computational power that limits their use in traditional general purpose processors using conventional software. The latest developments in field programmable gate arrays (FPGAs) provide an alternative for hardware and software co-design of complicated real-time vision algorithms. By tracking features from one frame to another, it becomes possible to perform many different high-level vision tasks, including object tracking and following. This thesis describes a vision guidance system for unmanned vehicles in general and the FPGA hardware implementation that operates vision tasks in real-time. This guidance system uses an object following algorithm to provide information that allows the UV to follow a target. The heart of the object following algorithm is real-time rank transform, which transforms the image into a more robust image that maintains the edges found in the original image. A minimum sum of absolute differences algorithm is used to determine the best correlation between frames, and the output of this correlation is used to update the tracking of the moving target. Control code can use this information to move the UV in pursuit of a moving target such as another vehicle.

No description available.

Modern nuclear and particle physics experiments run at a very high reaction rate and are able to deliver a data rate of up to hundred GBytes/s.  This data rate is far beyond the storage and on-line analysis capability. Fortunately physicists have only interest in a very small proportion among the huge amounts of data. Therefore in order to select the interesting data and reject the background by sophisticated pattern recognition processing, it is essential to realize an efficient data acquisition and trigger system which results in a reduced data rate by several orders of magnitude. Motivated by the requirements from multiple experiment applications, we are developing a high-end reconfigurable computation platform for data acquisition and triggering. The system consists of a scalable number of compute nodes, which are fully interconnected by high-speed communication channels. Each compute node features 5 Xilinx Virtex-4 FX60 FPGAs and up to 10 GBytesDDR2 memory. A hardware/software co-design approach is proposed to develop custom applications on the platform, partitioning performance-critical calculation to the FPGA hardware fabric while leaving flexible and slow controls to the embedded CPU plus the operating system. The system is expected to be high-performance and general-purpose for various applications especially in the physics experiment domain. As a case study, the particle track reconstruction algorithm for HADES has been developed and implemented on the computation platform in the format of processing engines. The Tracking Processing Unit (TPU) recognizes peak bins on the projection plane and reconstructs particle tracks in realtime. Implementation results demonstrate its acceptable resource utilization and the feasibility to implement the module together with the sys-tem design on the FPGA. Experimental results show that the online track reconstruction computation achieves 10.8 - 24.3 times performance acceleration per TPU module when compared to the software solution on a Xeon2.4 GHz commodity server. / QC 20101118

L'émergence d'une robotique médicale en chirurgie laparoscopique destinée à automatiser et améliorer la précision des interventions nécessite la mise en Suvre d'outils et capteurs miniaturisés intelligents dont la vision 3D temps réel est un des enjeux. Bien que les systèmes de vision 3D actuels représentent un intérêt certain pour des manipulations chirurgicales endoscopiques précises, ils ont l'inconvénient de donner une image 3D qualitative plutôt que quantitative, laquelle nécessite un appareillage spécifique rendant l'acte chirurgical inconfortable et empêche le couplage avec un calculateur dans le cadre d'une chirurgie assistée. Nous avons développé dans la cadre du projet interne « PICASO » (Plate-forme d'Intégration de CAméras multiSenOrielles) dont les enjeux scientifiques concernent le conditionnement de capteurs intégrés et le traitement et la fusion d'images multi spectrales, un dispositif de vision 3D compatible avec les temps d'exécution des actes chirurgicaux. Ce système est basé sur le principe de la stéréoscopie humaine et met en Suvre des algorithmes de stéréovision passive dense issus de la robotique mobile. Dans cette thèse nous présentons des architectures massivement parallèles, implémentées dans un circuit FPGA, et capables de fournir des images de disparité à la cadence de 130 trames/sec à partir d'images de résolution 640x480 pixels. L'algorithme utilisé est basé sur la corrélation Census avec une fenêtre de calcul de 7 x 7 pixels. Celui-ci a été choisi pour ses performances en regard de sa simplicité de mise en Suvre et la possibilité de paralléliser la plupart des calculs. L'objectif principal de cet algorithme est de rechercher, pour chaque point, la correspondance entre deux images d'entrées (droite et gauche) prises de deux angles de vue différents afin d'obtenir une "carte de disparités" à partir de laquelle il est possible de reconstruire la scène 3D. Pour mettre en Suvre cet algorithme et tenir les contraintes « temps réel » nous avons développé des architectures en « pipeline » (calcul des moyennes, transformation Census, recherche des points stéréo-correspondants, vérification droite-gauche, filtrage...). L'essentiel des différentes parties qui composent l'architecture est décrit en langage VHDL synthétisable. Enfin nous nous sommes intéressés à la consommation en termes de ressources FPGA (mémoires, macro-cellules) en fonction des performances souhaitées.