<p>In this thesis it is investigated if representing a field <i>Z</i><i>p</i><i>, p</i> = 1 (mod 4) prime, by another field <i>Z[i]</i>/ < <i>a + bi </i>> over the gaussian integers, with <i>p</i> = <i>a</i><i>2</i><i> + b</i><i>2</i>, results in arithmetic architectures using a smaller number of logic gates. Only bit parallell architectures are considered and the programs Espresso and SIS are used for boolean minimization of the architectures. When counting gates only NAND, NOR and inverters are used.</p><p>Two arithmetic operations are investigated, addition and multiplication. For addition the architecture over<i> Z[i]/ < a+bi ></i> uses a significantly greater number of gates compared with an architecture over<i> Z</i><i>p</i>. For multiplication the architecture using gaussian integers uses a few less gates than the architecture over <i>Z</i><i>p</i> for <i>p</i> = 5 and for<i> p</i> = 17 and only a few more gates when <i>p</i> = 13. Only the values 5, 13, 17 have been compared for multiplication. For addition 12 values, ranging from 5 to 525313, have been compared.</p><p>It is also shown that using a blif model as input architecture to SIS yields much better performance, compared to a truth table architecture, when minimizing.</p>

In this thesis it is investigated if representing a field Zp, p = 1 (mod 4) prime, by another field Z[i]/ &lt; a + bi &gt; over the gaussian integers, with p = a2 + b2, results in arithmetic architectures using a smaller number of logic gates. Only bit parallell architectures are considered and the programs Espresso and SIS are used for boolean minimization of the architectures. When counting gates only NAND, NOR and inverters are used. Two arithmetic operations are investigated, addition and multiplication. For addition the architecture over Z[i]/ &lt; a+bi &gt; uses a significantly greater number of gates compared with an architecture over Zp. For multiplication the architecture using gaussian integers uses a few less gates than the architecture over Zp for p = 5 and for p = 17 and only a few more gates when p = 13. Only the values 5, 13, 17 have been compared for multiplication. For addition 12 values, ranging from 5 to 525313, have been compared. It is also shown that using a blif model as input architecture to SIS yields much better performance, compared to a truth table architecture, when minimizing.

"Elliptic Curve Cryptosystems (ECCs) are utilized as an alternative to traditional public-key cryptosystems, and are more suitable for resource limited environments due to smaller parameter size. In this dissertation we carry out a thorough investigation of side-channel attack aware ECC implementations over finite fields of prime characteristic including the recently introduced Edwards formulation of elliptic curves, which have built-in resiliency against simple side-channel attacks. We implement Joye's highly regular add-always scalar multiplication algorithm both with the Weierstrass and Edwards formulation of elliptic curves. We also propose a technique to apply non-adjacent form (NAF) scalar multiplication algorithm with side-channel security using the Edwards formulation. Our results show that the Edwards formulation allows increased area-time performance with projective coordinates. However, the Weierstrass formulation with affine coordinates results in the simplest architecture, and therefore has the best area-time performance as long as an efficient modular divider is available."