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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Proposta e simulação de uma arquitetura RISC / Design and simulation of a RISC architecture

Valente, Fredy Joao 12 April 1991 (has links)
RISC - Uma nova tendência em arquitetura de computadores. Este trabalho apresenta um estudo de como surgiu esta nova arquitetura, e suas características básicas, que a diferencia das arquiteturas convencionais. Uma proposta de microprocessador RISC é apresentada, com sua rota de dados completamente detalhada. Um simulador para arquitetura RISC foi então construído, para se testar este microprocessador. Para validar o simulador, que é a idéia principal deste trabalho, e para se avaliar a arquitetura do microprocessador proposto, usou-se o benchmark Dhrystone, e os resultados foram comparados com máquinas comerciais. / RISC - A new trend in computer architecture. This work presents a study of how this new architecture emerged, and the basic caracteristics that diferentiate it from the conventional architectures. A proposed RISC microprocessor is presented with the completely detailed data-path. A simulator for the RIse architecture was built to test this microprocessor. To validate the simulator, which is the main idea of this work, and to evaluate the architecture of the proposed microprocessor, the Dhrystone benchmark was used and the results were compared with commercial machines.
2

Experimental analysis of a nonlinear moored structure

Narayanan, Suchithra 02 April 1999 (has links)
Graduation date: 1999
3

Contribution à l'étude des mouvements d'air dans le bâtiment à l'aide d'un code de champ application à la ventilation naturelle d'un local par une ou deux grandes ouvertures /

Regard, Muriel Guarracino, Gérard. January 2000 (has links)
Thèse doctorat : Conception en Bâtiment et Techniques Urbaines : Villeurbanne, INSA : 1996. / Titre provenant de l'écran-titre. Bibliogr. p. 204-208.
4

Implementing Kqml Agent Communication Language For Multiagent Simulation Architectures On Hla

Gokturk, Erek 01 January 2003 (has links) (PDF)
Multiagent simulation is gaining popularity due to its intuitiveness and ability in coping with domain complexity. HLA, being a distributed simulation architecture standard, is a good candidate for implementing a multiagent simulation infrastructure on, provided that agent communication can be implemented. HLA, being a standard designed towards a wide coverage of simulation system architectures and styles, is not an easy system to master. In this thesis, an abstraction layer called the Federate Abstraction Layer (FAL) is described for better engineering of software systems participating in an HLA simulation, providing lower project risks for the project manager and ease of use for the C++ programmers. The FAL is in use in project SAVMOS in Modelling and Simulation Laboratory. Discussion of FAL is followed by discussion of the study for realizing KQML for use in multiagent architectures to be built on top of HLA as the data transfer medium. The results are demonstrated with 10 federates implemented using the FAL.
5

Proposta e simulação de uma arquitetura RISC / Design and simulation of a RISC architecture

Fredy Joao Valente 12 April 1991 (has links)
RISC - Uma nova tendência em arquitetura de computadores. Este trabalho apresenta um estudo de como surgiu esta nova arquitetura, e suas características básicas, que a diferencia das arquiteturas convencionais. Uma proposta de microprocessador RISC é apresentada, com sua rota de dados completamente detalhada. Um simulador para arquitetura RISC foi então construído, para se testar este microprocessador. Para validar o simulador, que é a idéia principal deste trabalho, e para se avaliar a arquitetura do microprocessador proposto, usou-se o benchmark Dhrystone, e os resultados foram comparados com máquinas comerciais. / RISC - A new trend in computer architecture. This work presents a study of how this new architecture emerged, and the basic caracteristics that diferentiate it from the conventional architectures. A proposed RISC microprocessor is presented with the completely detailed data-path. A simulator for the RIse architecture was built to test this microprocessor. To validate the simulator, which is the main idea of this work, and to evaluate the architecture of the proposed microprocessor, the Dhrystone benchmark was used and the results were compared with commercial machines.
6

Data Mining On Architecture Simulation

Maden, Engin 01 March 2010 (has links) (PDF)
Data mining is the process of extracting patterns from huge data. One of the branches in data mining is mining sequence data and here the data can be viewed as a sequence of events and each event has an associated time of occurrence. Sequence data is modelled using episodes and events are included in episodes. The aim of this thesis work is analysing architecture simulation output data by applying episode mining techniques, showing the previously known relationships between the events in architecture and providing an environment to predict the performance of a program in an architecture before executing the codes. One of the most important points here is the application area of episode mining techniques. Architecture simulation data is a new domain to apply these techniques and by using the results of these techniques making predictions about the performance of programs in an architecture before execution can be considered as a new approach. For this purpose, by implementing three episode mining techniques which are WINEPI approach, non-overlapping occurrence based approach and MINEPI approach a data mining tool has been developed. This tool has three main components. These are data pre-processor, episode miner and output analyser.
7

Software Architecture Simulation : Performance evaluation during the design phase

Borowski, Jimmy January 2004 (has links)
Due to the increasing size and complexity of software systems, software architectures have become a crucial part in development projects. A lot of effort has been put into defining formal ways for describing architecture specifications using Architecture Description Languages (ADLs). Since no common ADL today offers tools for evaluating the performance, an attempt to develop such a tool based on an event-based simulation engine has been made. Common ADLs were investigated and the work was based on the fundamentals within the field of software architectures. The tool was evaluated both in terms of correctness in predictions as well as usability to show that it actually is possible to evaluate the performance using high-level architectures as models.
8

Efficient data structures for discovery in high level architecture (HLA)

Rahmani, Hibah 01 January 2000 (has links)
The High Level Architecture (HLA) is a prototype architecture for constructing distributed simulations. HLA is a standard adopted by the Department of Defense (DOD) for development of simulation environments. An important goal of the HLA is to reduce the amount of data routing between simulations during run-time. The Runtime Infrastructure (RTI) is an operating system that is responsible for data routing between the simulations in HLA. The data routing service is provided by the Data Distribution Manager of the RTI. Several methods have been proposed and used for the implementation of data distribution services. The grid-based filtering method, the interval tree method, and the quad-tree method are examples. This thesis analyzes and compares two such methods: the grid and the quad-tree, in regards to their use in the discovery of intersections of publications and subscriptions. The number of false positives and the CPU time of each method are determined for typical cases. For most cases, the quad-tree methos produces less false positives. This method is best suited for large simulations where the cost of maintaining false positives, or non-relevant entities, may be prohibitive. For most cases, the grid method is faster than the quad-tree method. This method may be better suited for small simulations where the host has the capacity to accommodate false positives. The results of this thesis can be used to decide which of the two methods is better suited to a particular type of simulation exercise.
9

An experimental investigation of dynamically reconfigurable computer network architectures through simulation

Venkateshwaran, Anjali 10 June 2012 (has links)
The research described in this thesis is divided conveniently into three components: (1) the credibility assessment of a simulation model for the investigation of dynamically reconfigurable computer network architectures, (2) a comparative study of the standardized time series method of simulation output analysis, and (3) an experimental comparison of the effects of dynamic reconfigurability on message transmission delays and network throughput. The credibility assessment relies almost completely on verification procedures applied to both communicative and program representations of the model. In the absence of an extant system, validation consists of extensive, program traces to assure that model behavior matches expectations and reflects no inconsistencies. Application of a standardized time series technique produces the advantages reported by other researchers with regard to sampling efficiency (information derived per sample unit) when dynamic reconfigurability is precluded. The inherent non-stationarity induced by reconfiguration reveals the sensitivity of standardized time series and the consequent adjustment to preserve coverage. A compromise between coverage and sampling efficiency prompts the choice of the batch means method for experimental comparison. Experimental comparison shows that under high traffic variability reconfigurability / Master of Science

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