In this thesis, we propose different CORDIC architectures which solve the problems of long-latency in traditional pipeline CORDIC and the large-area cost in table-based CORDIC. The original table-based CORDIC can be divided into two stages, coarse stage and fine stage. We also propose the three-stage architectures, composed of traditional pipeline CORDIC, Rom/Multiplier architecture and linear approximation. Detailed analysis and estimation in area and latency of these different two-stage and three-stage architectures with different bit accuracy are given in order to determine the best architecture design for a particular precision. Finally, we choose one of the architectures to implement, compare the results, and show its applications.

Functional evaluation is one of key arithmetic operations in many applications including 3D graphics and stereo. Among various designs of hardware-based function evaluation methods, piecewise polynomial approximation is the most popular approach which interpolates the piecewise function curve in a sub-interval using polynomials with polynomial coefficients of each sub-interval stored in an entry of a lookup table ROM. The conventional piecewise methods usually determine the bit-widths of each ROM entry, multipliers, and adders by analyzing the various error sources, including polynomial approximation errors, coefficient quantization errors, truncation errors of arithmetic operations, and the final rounding error. In this thesis, we present a new piecewise function evaluation design by considering all the error sources together. By combining all the error sources during the approximation, quantization, truncation and rounding, we can efficiently reduce the area cost of ROM and the corresponding arithmetic units in the design of CORDIC processors.