In this work, various components for low power RF telemetry applications have been investigated. These designed, fabricated and tested devices include radio frequency (RF) micro-electro-mechanical systems (MEMS) switches, single-pole-double-throw (SPDT) RF MEMS switches, nano fabricated capacitors and switching devices, and micromachined microstrip patch antennas.Coplanar waveguide (CPW) RF capacitive switches in shunt and series configuration were designed for high isolation, low insertion loss, and fast switching speed. Switches with > 35 dB isolation, < 0.3 dB insertion loss and switching speeds in the 10's of microseconds were fabricated and measured. These switches were packaged using photo-imagable resists and flip-chip bonding techniques. The MEMS shunt switch topology was also implemented into a single-pole-double-throw (SPDT) design by utilizing two such switches in a series and a shunt configuration, offset by a quarter wavelength section to provide a RF shor t at the input of the shunt switch in the off state. This type of design has the advantage of requiring a simple on-off (0 V and 35 V) bias supply to select the switch state.Also, the use of a focused ion beam (FIB) tool to mill sub-micron gaps in CPW transmission line structures was investigated. Nearly ideal capacitors in the micro- and mm- frequency range with capacitance of 8-12 fF were obtained using this milling technique. The FIB's capability to mill such small gaps at an oblique angle was also utilized to fabricate RF nano switches. These devices were switched with speeds of less than 300 ns with voltages of less than 20 V. Finally, solid state and packaged MEMS switches were integrated into a novel binary amplitude shift keyed (BASK) modulating RF telemetry system to provide the modulation of a redirected 10 GHz continuous wave (CW) signal. A pair of cross-polarized micromachined microstrip patch antennas was used in the system to receive the CW signal and re-transmit th e modulated signal. A transmission range of over 25 m was demonstrated with the solid state switch reflectenna.

La conception des futures générations de capteurs d'images CMOS, nécessite l'intégration de structures 3D telles que les tranchées profondes d'isolation, ou encore l'adoption de nouvelles architectures telles que les capteurs d'images à illumination face arrière. Cependant, l'intégration de telles architectures engendre l'apparition de nouvelles interfaces Si/SiO2, pouvant être la source d'un fort courant d'obscurité Idark, dégradant considérablement les performances électro-optiques du capteur. Ainsi, dans le but d'éliminer le Idark et d'augmenter l'efficacité de collecte et de confinement des photoporteurs au sein de la photodiode, la passivation de ces interfaces par l'introduction d'une jonction fortement dopée a été étudiée. D'une part, la passivation de la face arrière a été réalisée par implantation ionique activée par recuit laser pulsé. Grâce à un traitement très court et localisé, le recuit laser a démontré sa capacité à réaliser des jonctions minces et très abruptes. Une très bonne qualité cristalline ainsi que des taux d'activation avoisinant les 100% ont pu être atteint dans le mode fusion. Le mode sous-fusion quant à lui permet d'obtenir des résultats prometteurs en multipliant le nombre de tir laser. Les résultats électriques ont permis de distinguer les conditions optimales d'implantation et de recuit pour l'achèvement d'un faible niveau de Idark comparable à la référence en vigueur ainsi qu'une bonne sensibilité. Le deuxième axe d'étude s'est intéressé à la passivation des flancs des DTI par épitaxie sélective dopée in-situ. Des dépôts très uniformes de la cavité accompagnés d'une très bonne conformité de dopage le long des tranchées ont pu être réalisés. Les résultats sur lot électrique ont montré un très faible niveau de Idark supplantant la référence en vigueur / In order to maintain or enhance the electro-optical performances while decreasing the pixel size, advanced CMOS Image Sensors (CIS) requires the implementation of new architectures. For this purpose, deep trenches for pixel isolation (DTI) and backside illumination (BSI) have been introduced as ones of the most promising candidates. The major challenge of these architectures is the high dark current level (Idark) due to the generation/recombination centers present at both, DTI sidewalls and backside surfaces. Therefore, the creation of very shallow doped junctions at these surfaces reducing Idark and further crosstalk by drifting the photo-generated carriers to the photodiode region appears as key process step for introducing these architectures. For the backside surface passivation, a very shallow doped layer can be achieved by low-energy implantation followed by very short and localized heating provided by pulsed laser annealing (PLA). In the melt regime, box-shaped profiles with activation rates close to 100% and excellent crystalline quality have been achieved. The non-melt regime shows some potential, especially for multiple pulse conditions. In the optimal process conditions, very low level of Idark comparable to the standard reference has been achieved. In the other side, the passivation of DTI sidewalls has been performed by in-situ doped Epitaxy. Deposited layers with good uniformity and doping conformity all along the DTI cavity have been achieved. The electrical results show Idark values lower than the standard reference