Modern technology needs and advancements have introduced various new concepts such as Internet-of-Things, electric automotive, and Artificial intelligence. This implies an increased activity in the electronics domain of analog and high frequency. Silicon devices have emerged as a cost-effective solution for such diverse applications. As these silicon devices are pushed towards higher performance, there is a continuous need to improve fabrication, power efficiency, variability, and reliability. Often, a direct trade-off of higher performance is observed in the reliability of semiconductor devices. The acceleration-based methodologies used for reliability assessment are the adequate time-saving solution for the lifetime's extrapolation but come with uncertainty in accuracy. Thus, the efforts to improve the accuracy of reliability characterization methodologies run in parallel. This study highlights two goals that can be achieved by incorporating high-frequency characterization into the reliability characteristics. The first one is assessing high-frequency performance throughout the device's lifetime to facilitate an accurate description of device/circuit functionality for high-frequency applications. Secondly, to explore the potential of high-frequency characterization as the means of scanning reliability effects within devices. S-parameters served as the high-frequency device's response and mapped onto a small-signal model to analyze different components of a fully depleted silicon-on-insulator MOSFET. The studied devices are subjected to two important DC stress patterns, i.e., Bias temperature instability stress and hot carrier stress. The hot carrier stress, which inherently suffers from the self-heating effect, resulted in the transistor's geometry-dependent magnitudes of hot carrier degradation. It is shown that the incorporation of the thermal resistance model is mandatory for the investigation of hot carrier degradation. The property of direct translation of small-signal parameter degradation to DC parameter degradation is used to develop a new S-parameter based bias temperature instability characterization methodology. The changes in gate-related small-signal capacitances after hot carrier stress reveals a distinct signature due to local change of flat-band voltage. The measured effects of gate-related small-signal capacitances post-stress are validated through transient physics-based simulations in Sentaurus TCAD.:Abstract Symbols Acronyms 1 Introduction 2 Fundamentals 2.1 MOSFETs Scaling Trends and Challenges 2.1.1 Silicon on Insulator Technology 2.1.2 FDSOI Technology 2.2 Reliability of Semiconductor Devices 2.3 RF Reliability 2.4 MOSFET Degradation Mechanisms 2.4.1 Hot Carrier Degradation 2.4.2 Bias Temperature Instability 2.5 Self-heating 3 RF Characterization of fully-depleted Silicon on Insulator devices 3.1 Scattering Parameters 3.2 S-parameters Measurement Flow 3.2.1 Calibration 3.2.2 De-embedding 3.3 Small-Signal Model 3.3.1 Model Parameters Extraction 3.3.2 Transistor Figures of Merit 3.4 Characterization Results 4 Self-heating assessment in Multi-finger Devices 4.1 Self-heating Characterization Methodology 4.1.1 Output Conductance Frequency dependence 4.1.2 Temperature dependence of Drain Current 4.2 Thermal Resistance Behavior 4.2.1 Thermal Resistance Scaling with number of fingers 4.2.2 Thermal Resistance Scaling with finger spacing 4.2.3 Thermal Resistance Scaling with GateWidth 4.2.4 Thermal Resistance Scaling with Gate length 4.3 Thermal Resistance Model 4.4 Design for Thermal Resistance Optimization 5 Bias Temperature Instability Investigation 5.1 Impact of Bias Temperature Instability stress on Device Metrics 5.1.1 Experimental Details 5.1.2 DC Parameters Drift 5.1.3 RF Small-Signal Parameters Drift 5.2 S-parameter based on-the-fly Bias Temperature Instability Characterization Method 5.2.1 Measurement Methodology 5.2.2 Results and Discussion 6 Investigation of Hot-carrier Degradation 6.1 Impact of Hot-carrier stress on Device performance 6.1.1 DC Metrics Degradation 6.1.2 Impact on small-signal Parameters 6.2 Implications of Self-heating on Hot-carrier Degradation in n-MOSFETs 6.2.1 Inclusion of Thermal resistance in Hot-carrier Degradation modeling 6.2.2 Convolution of Bias Temperature Instability component in Hot-carrier Degradation 6.2.3 Effect of Source and Drain Placement in Multi-finger Layout 6.3 Vth turn-around effect in p-MOSFET 7 Deconvolution of Hot-carrier Degradation and Bias Temperature Instability using Scattering parameters 7.1 Small-Signal Parameter Signatures for Hot-carrier Degradation and Bias Temperature Instability 7.2 TCAD Dynamic Simulation of Defects 7.2.1 Fixed Charges 7.2.2 Interface Traps near Gate 7.2.3 Interface Traps near Spacer Region 7.2.4 Combination of Traps 7.2.5 Drain Series Resistance effect 7.2.6 DVth Correction 7.3 Empirical Modeling based deconvolution of Hot-carrier Degradation 8 Conclusion and Recommendations 8.1 General Conclusions 8.2 Recommendations for Future Work A Directly measured S-parameters and extracted Y-parameters B Device Dimensions for Thermal Resistance Modeling C Frequency response of hot-carrier degradation (HCD) D Localization Effect of Interface Traps Bibliography

Ce travail contribue à l'évaluation de la technique de génération de seconde harmonique induite par un champ électrique quasi statique, ou technique EFISHG, appliquée au domaine de la microélectronique. Une description du principe de la technique EFISHG, basé sur l'optique non linéaire, permet d'appréhender l'origine physique de cette méthode. Un état de l'art a permis d'identifier deux champs d'applications liés à la microélectronique : l'analyse de défaillance, via la mesure en temps réelle des variations de champs électriques internes dans les circuits intégrés, et la fiabilité par l'étude du piégeage de charges à l'interface Si/SiO2 et de la dégradation dite de " Negative Bias Temperature Instability " ou NBTI. Ce manuscrit présente les différentes étapes qui ont permis l'élaboration d'un banc de test en vue de l'évaluation de l'applicabilité de la technique EFISHG à ces problématiques. Les résultats expérimentaux obtenus avec ce montage ont permis de mettre en avant les possibilités qu'offre la technique EFISHG à caractériser et à accélérer le vieillissement NBTI.

Ce travail contribue à l’évaluation de la technique de génération de seconde harmonique induite par un champ électrique quasi statique, ou technique EFISHG, appliquée au domaine de la microélectronique. Une description du principe de la technique EFISHG, basé sur l’optique non linéaire, permet d’appréhender l’origine physique de cette méthode. Un état de l’art a permis d’identifier deux champs d’applications liés à la microélectronique : l’analyse de défaillance, via la mesure en temps de réelle des variations de champs électriques internes dans les circuits intégrés, et la fiabilité par l’étude du piégeage de charges à l’interface Si/SiO2 et de la dégradation dite de « Negative Bias Temperature Instability » ou NBTI. Ce manuscrit présente les différentes étapes qui ont permis l’élaboration d’un banc de test en vue de l’évaluation de l’applicabilité de la technique EFISHG à ces problématiques. Les résultats expérimentaux obtenus avec ce montage ont permis de mettre en avant les possibilités qu’offre la technique EFISHG à caractériser et à accélérer le vieillissement NBTI. / This work concerns the elaboration of an industrial method for Single Event Effect (SEE) sensitivity testing on integrated circuits. The concerned SEEs are those produced by heavy ions and are mainly Single Event Upset (SEU) and Single Event Latchup (SEL). The original test approach chosen in this study relies on the use of infrared laser pulses striking the backside of the tested device. Laser pulse and heavy ion interaction with semiconductor materials are described and a presentation of the particle accelerator test and some former laser test methods is also given. Advantages and drawbacks of those two techniques are discussed. The developed experimental setup uses a near infrared fiber coupled Neodyme/YAG pulsed laser. Its different elements are described. Using this tool to characterise the SEU sensitivity of several modern SRAMs has allowed to define a test methodology. Its efficiency is discussed and illustrated by different experimental results.