This thesis presents a new cascaded iterative VLSI sorting architecture that can accelerate data sorting of variable-length sequences. The proposed sorter mainly consists of a central data memory block, a core comparison unit, and a special address generation module. Many fast sorting algorithms can be represented by a network of compare-and-swap (C&S) operations which can be divided into several processing steps. Instead of using parallel C&S functional units to perform C&S operations of the same sorting step, our comparison unit is composed of cascaded C&S units connected through data commutator such that different sorting steps can be processed simultaneously. The advantage of cascaded architecture is that the number of data memory accesses can be reduced by a factor equal to the number of cascaded stages. However, how to reduce the overhead of the data commutator becomes the most critical design issue. This thesis has explored the feature of C&S operation order in Bitonic sorting such that much simpler and more regular data commutator module can be achieved compared with the previous cascade design derived based on Batcher sorting. Therefore, the cascade level of our sorter architecture can be more than 2. A sample of 4-level cascade sorter has been implemented in our thesis. To generate the address sequence suitable for the proposed cascaded comparison unit, this paper proposes a low-cost address generator design based on the bit-permutation technique. Although high cascade level can lead to significant reduction of memory access which can help reducing the power dissipation, the issues of low hardware utilization for short data sequences and the increasing commutator overhead cannot be neglected. Therefore, to achieve further speed-up, this paper also adopts another parallelism approach for data sorter design by utilizing block-level C&S units which can compare a block of data at the same time. The block-level C&S units can be designed based on traditional Batcher¡¦s sorting network. Based on the proposed Bitonic cascade and Batcher¡¦s block sorting approaches, very fast and low-power sorter hardware can be achieved.

The research in this thesis is focused on the problem of Block Sorting, which has applications in Computational Biology and in Optical Character Recognition (OCR). A block in a permutation is a maximal sequence of consecutive elements that are also consecutive in the identity permutation. BLOCK SORTING is the process of transforming an arbitrary permutation to the identity permutation through a sequence of block moves. Given an arbitrary permutation π and an integer m, the Block Sorting Problem, or the problem of deciding whether the transformation can be accomplished in at most m block moves has been shown to be NP-hard. After being known to be 3-approximable for over a decade, block sorting has been researched extensively and now there are several 2-approximation algorithms for its solution. This work introduces new structures on a permutation, which are called runs and ordered pairs, and are used to develop two new approximation algorithms. Both the new algorithms are 2-approximation algorithms, yielding the approximation ratio equal to the current best. This work also includes an analysis of both the new algorithms showing they are 2-approximation algorithms.

An implementation framework has been developed in this thesis for a well-known APX-hard combinatorial optimization problem known as Block Sorting. The motivation for the study of this problem comes from applications such as computational biology and optical character recognition. While existing Block Sorting research has been theoretically focused on the development and analysis of several approximation algorithms for Block Sorting, little or no work has been carried out thus far on the implementation of the proposed approximation algorithms. The conceptualization of an implementation framework and illustrating its use by experimenting with the existing approximation algorithms will provide means for discovering newer approaches to handling this important problem. As the main contribution, the research in this thesis provides a new greedy algorithm for Block Sorting in which each block move either reduces the number of blocks by two or three blocks, or reduces by one the number of reversals or inversions in the orig- inal permutation. Experimental results for all algorithms are also provided along with a comparison of their performance using the number of block moves and approximation ratios as performance metrics when sorting permutations of a given order, and as the order of permutations is varied. Preliminary results from the experimentation were shared at the 2017 IEEE 17th International Conference on Bioinformatics and Bioengineering (BIBE) [1]. To the best of our knowledge, this is the first work that has been focused on the implementation and experimental performance analysis of any algorithm for Block Sorting. We believe the results presented in this thesis will be useful for researchers and practitioners working in this area.