No description available.

Thesis (Ph. D.)--Washington State University, May 2009. / Title from PDF title page (viewed on June 19, 2009). "School of Electrical Engineering and Computer Science." Includes bibliographical references (p. 117-125).

No description available.

Thesis (M.S.)--University of Texas at Dallas, 2007. / Includes vita. Includes bibliographical references (leaves 42-43)

Thesis (M.S.)--Rochester Institute of Technology, 1992. / Typescript. Includes bibliographical references.

Thesis (M.S.)--Washington State University. / Includes bibliographical references.

Wong Wai-Chiu. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 94-101). / Abstracts in English and Chinese. / Abstract --- p.iii / Abstract in Chinese --- p.v / Acknowledgements --- p.vi / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivations --- p.2 / Chapter 1.2 --- Progress on Interconnect-driven Floorplanning --- p.4 / Chapter 1.2.1 --- Congestion Optimization --- p.4 / Chapter 1.2.2 --- Buffer Insertion --- p.5 / Chapter 1.3 --- Contributions --- p.6 / Chapter 1.4 --- Organization of this Thesis --- p.7 / Chapter 2 --- "VLSI Circuit Design, Physical Design Cycle and Floorplanning" --- p.8 / Chapter 2.1 --- VLSI Circuit Design Cycle --- p.9 / Chapter 2.2 --- Physical Design Cycle --- p.10 / Chapter 2.2.1 --- Circuit Partitioning --- p.10 / Chapter 2.2.2 --- Floorplanning and Placement --- p.11 / Chapter 2.2.3 --- Routing --- p.12 / Chapter 2.2.4 --- Compaction --- p.12 / Chapter 2.3 --- Introduction to Floorplanning --- p.13 / Chapter 2.4 --- Types of Floorplan --- p.14 / Chapter 2.5 --- Simulated Annealing --- p.15 / Chapter 2.6 --- Floorplan Representation --- p.16 / Chapter 2.6.1 --- Polish Expression --- p.17 / Chapter 2.6.2 --- Sequence Pair --- p.18 / Chapter 2.6.3 --- Twin Binary Tree --- p.20 / Chapter 2.6.4 --- Comparisons between Different Floorplan Representations --- p.21 / Chapter 2.7 --- Chapter Summary --- p.22 / Chapter 3 --- Interconnect Optimization in Floorplanning --- p.24 / Chapter 3.1 --- Routing Congestion Optimization --- p.25 / Chapter 3.2 --- Buffer Planning --- p.26 / Chapter 3.3 --- Wire Sizing --- p.28 / Chapter 3.4 --- Simultaneous Wire Sizing and Buffer Planning --- p.30 / Chapter 3.5 --- Literature Review on Interconnect-driven Floorplanning --- p.31 / Chapter 3.5.1 --- Congestion Optimization --- p.31 / Chapter 3.5.2 --- Buffer Insertion --- p.36 / Chapter 3.6 --- Chapter Summary --- p.40 / Chapter 4 --- Floorplanning with Congestion Optimization and Buffer Block Planning --- p.41 / Chapter 4.1 --- Floorplanner Overview --- p.42 / Chapter 4.1.1 --- Grid Structure and Blocked Grids --- p.44 / Chapter 4.1.2 --- Buffer Block Planning --- p.44 / Chapter 4.2 --- Elmore Delay Model --- p.46 / Chapter 4.2.1 --- Wire Sizing --- p.47 / Chapter 4.2.2 --- Buffer Insertion --- p.48 / Chapter 4.2.3 --- Simultaneous Buffer Insertion and Wire Sizing --- p.49 / Chapter 4.3 --- Dynamic Programming Approach for Buffer Planning and Wire Sizing --- p.49 / Chapter 4.4 --- Implementation of the Dynamic Programming Approach --- p.51 / Chapter 4.5 --- Lookup Table Construction --- p.53 / Chapter 4.6 --- Congestion Model --- p.55 / Chapter 4.7 --- Cost Function --- p.56 / Chapter 4.8 --- Algorithm --- p.56 / Chapter 4.9 --- Experimental Results --- p.57 / Chapter 4.9.1 --- Experimental Results on Simultaneous Buffer Insertion and Wire Sizing --- p.57 / Chapter 4.9.2 --- Experimental Results of using the Table Lookup Approach --- p.58 / Chapter 4.10 --- Chapter Summary --- p.60 / Chapter 5 --- Floorplanning with Flexible Buffer Planning and Routability Op- timization --- p.63 / Chapter 5.1 --- Floorplanner Overview --- p.64 / Chapter 5.1.1 --- Constraints in Buffer Locations --- p.64 / Chapter 5.2 --- Congestion Estimation --- p.66 / Chapter 5.3 --- Buffer Location Computation --- p.67 / Chapter 5.3.1 --- Feasible Locations for Buffer Insertion --- p.67 / Chapter 5.3.2 --- Cost of Grids for Buffer Insertion --- p.69 / Chapter 5.3.3 --- Dynamic Programming Approach for Selecting Buffer Lo- cation of a Net --- p.70 / Chapter 5.3.4 --- An Example --- p.70 / Chapter 5.4 --- Congestion Model --- p.72 / Chapter 5.4.1 --- Net-count Congestion Model --- p.72 / Chapter 5.4.2 --- Grid-count Congestion Model --- p.74 / Chapter 5.5 --- Buffer Location Bounds --- p.75 / Chapter 5.6 --- Net Grouping --- p.77 / Chapter 5.7 --- Cost Function --- p.79 / Chapter 5.8 --- Algorithm . --- p.79 / Chapter 5.9 --- Experimental Results --- p.79 / Chapter 5.9.1 --- Net Grouping Factor --- p.80 / Chapter 5.9.2 --- Experimental Results of our Floorplanner --- p.80 / Chapter 5.9.3 --- Comparison on Different Congestion Models --- p.82 / Chapter 5.10 --- Chapter Summary --- p.83 / Chapter 6 --- Conclusion --- p.86 / Chapter 6.1 --- Discussion --- p.87 / Chapter 6.2 --- Improvements --- p.88 / Chapter 6.2.1 --- Net Grouping and Ordering --- p.88 / Chapter 6.2.2 --- Congestion Modelling --- p.89 / Appendix --- p.90 / Chapter A --- Overview on VLSI Technology --- p.91 / Chapter A.l --- Moore's Law and Trends in VLSI --- p.91 / Chapter A.2 --- Scaling --- p.93 / Bibliography --- p.101

by Chung-Leung, Chiu. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1996. / Includes bibliographical references (leaves 110-113). / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Partial Basic Block Storing Mechanism --- p.1 / Chapter 1.2 --- Data-Tagged Mechanism in Branch Target Buffer --- p.4 / Chapter 1.3 --- Organization of the dissertation --- p.5 / Chapter 2 --- Related Research --- p.7 / Chapter 2.1 --- Branch Prediction --- p.7 / Chapter 2.2 --- Branch History Table --- p.8 / Chapter 2.2.1 --- Performance of Branch History Table in reducing the Branch Penalty --- p.10 / Chapter 2.3 --- Branch Target Cache --- p.10 / Chapter 2.4 --- Early Resolution of Branch --- p.11 / Chapter 2.5 --- Software Inter-block Reorganization --- p.12 / Chapter 2.6 --- Branch Target Buffer --- p.13 / Chapter 2.7 --- Data Prefetching --- p.16 / Chapter 2.7.1 --- Software-Directed Prefetching --- p.16 / Chapter 2.7.2 --- Hardware-based prefetching --- p.17 / Chapter 3 --- New Branch Target Buffer Design --- p.19 / Chapter 3.1 --- Alternate Line Storing --- p.22 / Chapter 3.2 --- Storing More Than One Line On Entering The Dynamic Basic Block --- p.27 / Chapter 4 --- Simulation Environment for New Branch Target Buffer Design --- p.30 / Chapter 4.1 --- Architectural Models and Assumptions --- p.30 / Chapter 4.2 --- Memory Models --- p.33 / Chapter 4.3 --- Evaluation Methodology and Measurement Criteria --- p.34 / Chapter 4.4 --- Description of the Traces --- p.35 / Chapter 4.5 --- Effect of the limitation of ATOM on the statistics of SPEC92 Bench- marks --- p.35 / Chapter 4.6 --- Environments for collecting relevant statistics of SPEC92 Benchmarks --- p.36 / Chapter 5 --- Results for New Branch Target Buffer Design --- p.38 / Chapter 5.1 --- Statistical Results and Analysis for SPEC92 Benchmarks --- p.38 / Chapter 5.2 --- Overall Performance --- p.39 / Chapter 5.3 --- Bus Latency Effect --- p.42 / Chapter 5.4 --- Effect of Cache Size --- p.45 / Chapter 5.5 --- Effect of Line Size --- p.47 / Chapter 5.6 --- Cache Set Associativity --- p.50 / Chapter 5.7 --- Partial Hits --- p.50 / Chapter 5.8 --- Prefetch Accuracy --- p.53 / Chapter 5.9 --- Effect of Prefetch Buffer Size --- p.54 / Chapter 5.10 --- Effect of Storing More Than One Line on Entry of New Dynamic Basic Block --- p.56 / Chapter 6 --- Data References Tagged into Branch Target Buffer --- p.60 / Chapter 6.1 --- Branch History Table Tagged Mechanism --- p.60 / Chapter 6.2 --- Lookahead Technique --- p.65 / Chapter 6.3 --- Default Prefetches Vs Data-tagged Prefetches --- p.71 / Chapter 6.4 --- New Priority Scheme --- p.73 / Chapter 7 --- Architectural Model for Data-Tagged References in Branch Target Buffer --- p.74 / Chapter 7.1 --- Architectural Models and Assumptions --- p.76 / Chapter 7.2 --- Memory Models --- p.79 / Chapter 7.3 --- Evaluation Methodology and Measurement Criteria --- p.79 / Chapter 7.4 --- Description of the Traces --- p.80 / Chapter 7.5 --- Environments for collecting relevant statistics of SPEC92 Benchmarks --- p.80 / Chapter 8 --- Results for Data References Tagged into Branch Target Buffer --- p.82 / Chapter 8.1 --- Statistical Results and Analysis --- p.82 / Chapter 8.2 --- Overall Performance --- p.83 / Chapter 8.3 --- Effect of Branch Prediction --- p.85 / Chapter 8.4 --- Effect of Number of Tagged Registers --- p.87 / Chapter 8.5 --- Effect of Different Tagged Positions in Basic Block --- p.90 / Chapter 8.6 --- Effect of Lookahead Size --- p.91 / Chapter 8.7 --- Prefetch Accuracy --- p.93 / Chapter 8.8 --- Cache Size --- p.95 / Chapter 8.9 --- Line Size --- p.96 / Chapter 8.10 --- Set Associativity --- p.97 / Chapter 8.11 --- Size of Branch History Table --- p.99 / Chapter 8.12 --- Set Associativity of Branch History Table --- p.99 / Chapter 8.13 --- New Priority Scheme Vs Default Priority Scheme --- p.102 / Chapter 8.14 --- Effect of Prefetch-On-Miss --- p.103 / Chapter 8.15 --- Memory Latency --- p.104 / Chapter 9 --- Conclusions and Future Research --- p.106 / Chapter 9.1 --- Conclusions --- p.106 / Chapter 9.2 --- Future Research --- p.108 / Bibliography --- p.110 / Appendix --- p.114 / Chapter A --- Statistical Results - SPEC92 Benchmarks --- p.114 / Chapter A.1 --- Definition of Abbreviations and Terms --- p.114

The optimal allocation of buffers in serial production systems is one of the oldest and most researched problems in Industrial Engineering. In general, there are three main approaches to the buffer allocation problem when the objective is to maximize throughput. The first is basically a systematic trial and error procedure supported either by discrete event simulation or analytical models. A second approach is to allocate buffers based on general design rules that have been established in the research literature through experimentation. And the third approach is to apply a buffer allocation optimization algorithm to a specific production line. All these approaches have limitations and could be time and resource consuming. Additionally, most of the existing research on buffer allocation only considers production systems modeled with an infinite supply of raw materials before the first workstation and an unlimited capacity for finished goods after the last workstation. In reality many production systems are designed as closed systems where an interaction between the last and the first workstations in the line is present. In a closed production system, there is a finite buffer after the last workstation and the number of "carriers" holding jobs that move through the line is fixed. The objective of this thesis was to develop efficient heuristic algorithms for the buffer allocation problem in closed production systems. Two heuristics for buffer allocation were implemented. Heuristic H 1 uses the idea that highly utilized workstation stages require any available buffer more than sub-utilized stages. Heuristic H2 uses information stored in the longest path of a network representation of job flow to determine where additional buffers are most beneficial. An experiment was designed to determine if there are any statistically significant differences between throughput values with buffer allocations obtained with a genetic algorithm, also developed in this research, and through puts with buffer allocations generated by Hi and H2. Several types of closed production systems were examined in eight different test cases. No significant differences in performance were observed. The efficiency of the heuristics was also analyzed. A significant difference between the speeds of Hi and H2 is found. The analysis performed in this research indicates that heuristic H2 is sufficiently effective and accurate for determining near optimal buffer allocations in closed production systems. / Graduation date: 2005

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003. / Includes bibliographical references (leaves 77-79). Also available in electronic version. Access restricted to campus users.