No description available.

FPGA fault recovery techniques, such as bitstream scrubbing, are only limited to detecting and correcting soft errors that corrupt the configuration memory. Scrubbing and related techniques cannot detect permanent faults within the FPGA fabric, such as short circuits and open circuits in FPGA transistors that arise from electromigration effects. Several Built-In Self-Test (BIST) techniques have been proposed in the past to detect and isolate such faults. These techniques suffer from routing congestion problems in modern FPGAs that have a large number of logic blocks. This thesis presents an improved BIST architecture for all Xilinx 7-Series FPGAs that is scalable to large arrays. The two primary sources of overhead associated with FPGA BIST, the test time and the memory required for storing the BIST configurations, are also reduced when compared to previous FPGA-BIST approaches. The BIST techniques presented here also eliminate the need for using any of the user I/O pins, such as a clock, a reset, and test observation pins; therefore, it is suitable for immediate deployment on any system with Xilinx 7-Series FPGAs. With faults detected, isolated, and corrected, the effective MTBF of a system can be extended. / Master of Science

Thesis--Auburn University, 2009. / Abstract. Vita. Includes bibliographic resources (p.88-89).

Master of Science / Department of Electrical Engineering / William Kuhn / When enough charges accumulate on two objects, the air dielectric between them breaks down to create a phenomenon known as electrostatic discharge (ESD). ESD is of great concern in the integrated circuit industry because of the damage it can cause to ICs. The problem will only become worse as process components become smaller. The three main types of ESD experienced by an IC are the human body model (HBM), the charged device model (CDM), and the machine model (MM). HBM ESD has the highest voltage while CDM ESD has the highest bandwidth and current of the three ESD types. Integrated circuits generally include ESD protection circuitry connected to their pads. Pads are the connection between the IC and the outside world, making them the required location for circuitry designed to route ESD events away from the IC's internal circuitry. The most basic protection pads use diodes connected from I/O to VDD and I/O to ground. A voltage clamp between VDD and ground is also necessary to protect against CDM and MM event types where the device may not yet have a low impedance supply path connected. The purpose of this research is to investigate the performance of ESD circuits and to develop a method for detecting the occurrence of an ESD event in an integrated circuit by utilizing IC fuses. The combination of IC fuses and detection circuitry designed to sense a broken fuse allows the IC to perform a built-in self-test (BIST) for ESD to identify compromised ICs, preventing manufacturers from shipping damaged circuits. Simulations are used to design an optimized protection circuit to complement the proposed ESD detection circuit. Optimization of an ESD pad circuit increases the turn-on speed of its voltage clamps and decreases the series resistance of its protection diodes. These improvements minimize the stress voltage placed on internal circuitry due to an ESD event. An ESD measurement setup is established and used to verify voltage clamp operation. This research also proposes an ESD detection circuit based on IC fuses, which fail during an ESD event. A variety of IC fuses are tested using the ESD measurement setup as well as a TLP setup in order to determine the time and current needed for them to break. Suitable IC fuses have a resistance less than 5 Ω and consistently break during the first trial.

<p>The technological development is enabling production of increasingly complex electronic systems. All those systems must be verified and tested to guarantee correct behavior. As the complexity grows, testing is becoming one of the most significant factors that contribute to the final product cost. The established low-level methods for hardware testing are not any more sufficient and more work has to be done at abstraction levels higher than the classical gate and register-transfer levels. This thesis reports on one such work that deals in particular with high-level test generation and design for testability techniques.</p><p>The contribution of this thesis is twofold. First, we investigate the possibilities of generating test vectors at the early stages of the design cycle, starting directly from the behavioral description and with limited knowledge about the final implementation architecture. We have developed for this purpose a novel hierarchical test generation algorithm and demonstrated the usefulness of the generated tests not only for manufacturing test but also for testability analysis.</p><p>The second part of the thesis concentrates on design for testability. As testing of modern complex electronic systems is a very expensive procedure, special structures for simplifying this process can be inserted into the system during the design phase. We have proposed for this purpose a novel hybrid built-in self-test architecture, which makes use of both pseudorandom and deterministic test patterns, and is appropriate for modern system-on-chip designs. We have also developed methods for optimizing hybrid built-in self-test solutions and demonstrated the feasibility and efficiency of the proposed technique.</p> / Report code: LiU-Tek-Lic-2002:46.

Thesis (M.S.)--Auburn University, 2008. / Abstract. Vita. Includes bibliographical references (p. 104-106).

Thesis(M.S.)--Auburn University, 2004. / Abstract. Vita. Includes bibliographic references (p.123-125).

Thesis--Auburn University, 2009. / Abstract. Vita. Includes bibliographical references (p. 112-113).

Nürnberg, University, Diss., 2004--Erlangen.

Cette thèse vise l’étude de nouvelles architectures d’auto test pour les convertisseurs de type pipeline. En production, les convertisseurs sont testés en fonctionnement statique et dynamique. Les techniques de test statique de linéarité sont les techniques les plus coûteuses durant la phase de production. La mesure des performances statiques utilise un stimulus à haute linéarité et très basse fréquence et la méthode de l’histogramme, nécessitant la collecte d’un grand nombre d’échantillons en sortie afin de moyenner le bruit. Ainsi, la quantité de données nécessaire augmente exponentiellement avec la résolution du CAN sous test. Pour cette raison, la réduction du temps de test des CANs est un domaine de recherche qui attire de plus en plus d’attention. Récemment, des nouvelles solutions ont été mises au point pour réduire de façon importante le temps de test, mais aucune solution d’auto test considérant un générateur de signal de haute résolution en combinaison avec une technique d'analyse intégrée, réduisant considérablement la quantité de données, n’a encore été développée. Dans le cadre de cette thèse, on envisage l’étude de techniques d’auto test statique pour ce type de convertisseurs. En particulier, cette thèse présente un générateur de stimulus de test intégré à haute linéarité et une technique modifiée de servo-loop qui, en combinaison avec un algorithme de test de linéarité avec réduction de codes, conduit à la définition d'une stratégie efficace et précise de test intégré pour les CANs de type pipeline. La thèse inclut la validation expérimentale des techniques proposées, en coopération avec ST Microelectronics, Grenoble. / This PhD thesis is aimed at exploring new Built-In-Self-Test (BIST) techniques for static linearity characterization of pipeline ADCs. During the production phase, the static and dynamic performances of the ADCs are tested. Static linearity test techniques are one of the more expensive test procedures that are performed at production line. The measurement of the static linearity performance requires the application of a low frequency high linearity stimulus and the collection of a high volume of output samples for noise averaging, usually using a histogram-based test setup. Thus, as the resolution of state-of-the-art ADCs increases, test time for static linearity characterization increases exponentially. For this reason, the reduction of the ADC test time is a hot topic that has gained an increasing interest over the past years. New techniques have recently been proposed to effectively reduce test time, but no BIST technique has yet been developed that considers a high resolution signal generator in combination with an on-chip analysis technique that dramatically reduces the amount of data. In this thesis, static linearity BIST techniques will be investigated for pipeline ADCs. In particular, this thesis presents a novel high-linearity on-chip test stimulus generator and a modified servo-loop technique that, in combination with reduced-code linearity test algorithms, lead to the definition of an efficient and accurate BIST strategy for pipeline ADCs. The work includes the experimental validation of the proposed techniques in collaboration with STMicroelectronics, Grenoble.