La miniaturisation des transistors MOSFETs sur silicium massif présente de nombreux enjeux en raison de l'apparition de phénomènes parasites. Notamment, la réduction de la surface des dispositifs entraîne une dégradation de la variabilité de leurs caractéristiques électriques. La technologie planaire totalement désertée, appelée communément FDSOI (pour Fully Depleted Silicon on Insulator), permet d'améliorer le contrôle électrostatique de la grille sur le canal de conduction et par conséquent d'optimiser les performances. De plus, de par la présence d'un canal non dopé, il est possible de réduire efficacement la variabilité de la tension de seuil des transistors. Cela se traduit par un meilleur rendement et par une diminution de la tension minimale d'alimentation des circuits SRAM (pour Static Random Access Memory). Une étude détaillée de la variabilité intrinsèque à cette technologie a été réalisée durant ce travail de recherche, aussi bien sur la tension de seuil (VT) que sur le courant de drain à l'état passant (ISAT). De plus, le lien existant entre la fluctuation des caractéristiques électriques des transistors et des circuits SRAM a été expérimentalement analysé en détail. Une large partie de cette thèse est enfin dédiée à l'investigation de la source de variabilité spécifique à la technologie FDSOI : les fluctuations de l'épaisseur du film de silicium. Un modèle analytique a été développé durant cette thèse afin d'étudier l'influence des fluctuations locales de TSi sur la variabilité de la tension de seuil des transistors pour les nœuds technologiques 28 et 20nm, ainsi que sur un circuit SRAM de 200Mb. Ce modèle a également pour but de fournir des spécifications en termes d'uniformité σTsi et d'épaisseur moyenne µTsi du film de silicium pour les prochains nœuds technologiques. / The scaling of bulk MOSFETs transistors is facing various difficulties at the nanometer era. The variability of the electrical characteristics becomes a major challenge which increases as the device dimensions are scaled down. Fully-Depleted Silicon On Insulator (FDSOI) technology, developed as an alternative to bulk transistors, exhibits a better electrostatic immunity which enables higher performances. Moreover, the reduction of the Random Dopant Fluctuation allows excellent variability immunity for the FDSOI technology due to its undoped channel. It leads to a yield enhancement and a reduction of the minimum supply voltage of SRAM circuits. The variability has been analyzed deeply during this thesis in this technology, both on the threshold voltage (VT) and on the ON-state current (ISAT). The correlation between the electrical characteristics of MOSFETs devices (i.e., the threshold voltage and the standard deviation σVT) and SRAM cells (i.e., the SNM and σSNM) has been investigated thanks to an extensive experimental study and modeling. This purpose of this thesis is also to analyze the specific FDSOI variability source: silicon thickness fluctuations. An analytical model has been developed in order to quantify the impact of local TSi variations on the VT variability for 28 and 20nm technology nodes, as well as on a 200Mb SRAM array. This model also enables to evaluate the silicon thickness mean (µTsi) and standard deviation (σTsi) specifications for next technology nodes.

To investigate quantum confinement effects on silicon (Si) light source electroluminescence (EL) properties like quantum efficiency, external power efficiency and spectral emission, thin Si finger junctions with nanometre-scale dimensions were designed and manufactured in a fully customized silicon-on-insulator (SOI) semiconductor production technology. Since commonly available photolithography is unusable to consistently define and align nanometre-scale line-widths accurately and electron-beam lithography (EBL) by itself is too time-expensive to expose complete wafers, the wafer manufacturing process employed a selective combination of photolithography and EBL. The SOI wafers were manufactured in the clean-rooms of both the Carl and Emily Fuchs Institute for Microelectronics (CEFIM) at the University of Pretoria (UP) and the Georgia Institute of Technology’s Microelectronic Research Centre (MiRC), which made a JEOL JBX-9300FS electron-beam pattern generator (EPG) available. As far as is known this was the first project in South Africa (and possibly at the MiRC) that employed EBL to define functional nanometre-scale semiconductor devices. Since no standard process recipe could be employed, the complete design and manufacturing process was based on self-obtained equipment characterization data and material properties. The manufacturing process was unprecedented in both the CEFIM and MiRC clean-rooms. The manufacture of nanometre-scale Si finger junctions not only approached the manufacturing limits of the employed processing machinery, but also had to overcome undesirable physical effects that in larger-scale semiconductor manufacture usually are negligible. The device design, mask layout and manufacturing process therefore had to incorporate various material, equipment limitation and physical phenomena like impurity redistribution occurring during the physical manufacturing process. Although the complicated manufacturing process allowed many unexpected problems to occur, it was expected that at least the simple junction breakdown devices be functional and capable of delivering data regarding quantum confinement effects. Although due to design and processing oversights only 29 out of 505 measured SOI light sources were useful light emitters, the design and manufacture of the SOI light sources was successful in the sense that enough SOI light sources were available to conduct useful optical characterization measurements. In spite of the fact that the functional light sources did not achieve the desired horizontal (width) confinement, measured optical spectra of certain devices indicate that vertical (thickness) confinement had been achieved. All spectrometer-measured thickness-confined SOI light sources displayed a pronounced optical power for 600 nm < λ < 1 μm. The SOI light source with the highest optical power output emitted about 8 times more optical power around λ = 850 nm than a 0.35 μm bulk-CMOS avalanche light-source operating at the same current. Possible explanations for this effect are given. It was shown that the buried oxide (BOX) layer in a SOI process could be used to reflect about 25 % of the light that would usually be lost to downward radiation back up, thereby increasing the external power efficiency of SOI light sources. This document elaborates on the technical objectives, approach, chip and process design, physical wafer manufacture, production process control and measurement of the nanometre-scale SOI light sources. Copyright / Dissertation (MEng)--University of Pretoria, 2010. / Electrical, Electronic and Computer Engineering / unrestricted