This work presents a new wireless Visible Light Communication lighting system targeted to future Smart Buildings. A digitally controlled LLC resonant dc-dc converter targeted to white LED luminaires is demonstrated. Visible Light Communication is implemented with minimal incremental cost, by operating the LLC converter in burst mode, without causing any visible disturbance. The converter operates with a regulated average LED current by adjusting the switching frequency, while the burst pulse timing is controlled to minimize the current disturbance and minimize the value of the output capacitor. Variable Pulse Position Modulation is used to modulate the data, while supporting a range of dimming settings. A digital demodulation scheme that supports variable frequency transmission is demonstrated. The 80 W, 400 V to 23 V converter experimental prototype has a peak efficiency of 93.8 %. The bit error rate of the complete system is fully characterized versus distance and angle.

This work presents a new wireless Visible Light Communication lighting system targeted to future Smart Buildings. A digitally controlled LLC resonant dc-dc converter targeted to white LED luminaires is demonstrated. Visible Light Communication is implemented with minimal incremental cost, by operating the LLC converter in burst mode, without causing any visible disturbance. The converter operates with a regulated average LED current by adjusting the switching frequency, while the burst pulse timing is controlled to minimize the current disturbance and minimize the value of the output capacitor. Variable Pulse Position Modulation is used to modulate the data, while supporting a range of dimming settings. A digital demodulation scheme that supports variable frequency transmission is demonstrated. The 80 W, 400 V to 23 V converter experimental prototype has a peak efficiency of 93.8 %. The bit error rate of the complete system is fully characterized versus distance and angle.

This thesis presents two contributions in the area of high speed clock and data recovery systems. These contributions are focused on the fast phase recovery and adaptive equalization techniques. The first contribution of this thesis is an adaptive engine for a 2x blind sampling receiver. The proposed adaptation engine is able to find the phase-dependent DFE coefficients of the receiver on the fly. The second contribution is a burst-mode clock and data recovery architecture which uses an analog phase interpolator. The proposed burst-mode CDR is capable of locking to the first data transition it receives. The phase interpolator uses the inherent timing information in the data transition to rotate the phase of a reference clock and align it with the incoming data edge. The feasibility of the concept is demonstrated through fabrication and measurements.

This thesis presents an analysis of the Modified Cramer Rao Bound (MCRB) for synchroniser performance in burst mode communication applications. This is accomplished by introducing the topic of burst mode communications and its practical applications, discussing the importance of synchronisation, presenting a model through which the mathematical analysis of this thesis is based upon, deriving a set of equations which can be used to calculate the MCRB and finally by performing various calculations of the MCRB with different parameters to examine their effects on the MCRB. The methods presented in this thesis are different from those presented in existing literature, which generally do not address the issue of burst mode synchronisation directly. The differences between the methods presented in this thesis and those of existing literature is also discussed.