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In the recent year, System-on-Chip (SoC) has become a popular and important issue. As the environment of the SoC design becomes more and more complex. The issue of system verification becomes more important. In previous, the intellectual property (IP) was developed dependently. Every designer just designed the IP without integrated with others. But with the complexity of the environment increasing, more and more IPs are integrated into a system. Even though the verification plans are more complex, but some protocol errors can also not found by designers. Some incautious behavior may cause the system deadlock or in a jam. Some research use protocol checker to verify bus protocol, but they can¡¦t synthesize, so we propose a rule-based and synthesizable style protocol checker(AXIChecker) to verify the transactions on the AXI bus conform the AMBA 3.0(AXI) protocol or not.

Tracing represents that the information which are generated from the system can be collected for later observation and analysis. Because the SoC design becomes more and more complex, an advanced tracing is needed instead of processor tracing only. However, the generation rate and the size of real time system traces are so huge such that the compressor for tracing is needed. In this thesis, we purpose an on-chip bus trace analyzer for SoC¡¦s. This trace analyzer can allowed to perform accurate, successive trace collection in an unlimited time and can be used in various embedded system without influencing the operation of the bus system. The approach consists of two stages: (1) timing/signal abstraction stage and (2) trace reducing stage. And we show how to design and implement the on-chip bus trace analyzer. It can be also configured by users for different debugging uses. The experimental results show that this bus trace analyzer can reach a good compression ratio of 99% for AMBA system. Hence, by utilizing this trace analyzer, the support for debugging can be more powerful than existing method.

In the System on a Chip () era, more components are embedded in one chip. Therefore, it has been an important issue to assist verification and debugging by observing the signals inside of a chip. The bus signals tracing is a general method to resolve it. However, the quantities of signals that have to be traced in an are very huge, we must to reduce the trace data as more as possible. Because of the reasons described as above, we propose a hardware called multi-resolution bus tracer to overcome these problems in this thesis. In the bus tracer, user can changes the observed accuracy of tracing signals dynamically during the program execution, and reduces all those signals efficiently. The experiment results show that bus tracer can achieve 85% average compressed ratio on the forward tracing, and 84% average compressed ratio on the backward tracing. In the other hand, the software called trace data analyzer not only transfers the trace signals into Value Change Dump (VCD) file format but also provides some essential analyses for user observation. Finally, our IP (Intelligent Property) has been integrated into a real platform: 3D Graphics Acceleration, and tape-out successfully. Therefore, using the multi-resolution bus trace analyzer can promote the abilities of system debugging efficiently.

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003. / Includes bibliographical references (leaves 89-90). Also available in electronic version. Access restricted to campus users.

No description available.

Thesis (MEng)--University of South Australia, 2000

Stuttgart, Univ., Fachstudie, 2007.

Thesis (M. Sc.)--University of Hong Kong, 1999. / Includes bibliographical references (leaves 119-123).

Thesis (M.A.)--University of Hong Kong, 2002. / Includes bibliographical references (leaves 90-92).