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In a System on a Chip (SoC), interconnect is the factor limiting Performance, Power, Area and Schedule (PPAS). Distributed crossbar switches also called as Switching Central Resources (SCR) are often used to implement high performance interconnect in a SoC – Network on a Chip (NoC). Multiple issue bus protocols like AXI (from ARM), VBUSM (from TI) are used in paths critical to the performance of the whole chip. Experimental analysis of effects on PPAS by architectural modifications to the SCRs is carried out, using synthesis tools and Texas Instruments (TI) in house power estimation tools. The effects of scaling of SCR sizes are discussed in this report. These results provide a quick means of estimation for architectural changes in the early design phase. Apart from SCR design, the other major domain, which is a concern, is deadlocks. Deadlocks are situations where the network resources are suspended waiting for each other. In this report various kinds of deadlocks are classified and their respective mitigations in such networks are provided. These analyses are necessary to qualify distributed SCR interconnect, which uses multiple issue protocols, across all scenarios of transactions. The entire analysis in this report is carried out using a flagship product of Texas Instruments. This ASIC SoC is a complex wireless base station developed in 2010- 2011, having 20 major cores. Since the parameters of crossbar switches with multiple issue bus protocols are commonly used in SoCs across the semiconductor industry, this reports provides us a strong basis for architectural/design selection and validation of all such high performance device interconnects. This report can be used as a seed for the development of an interface tool for architects. For a given architecture, the tool suggests architectural modifications, and reports deadlock situations. This new tool will aid architects to close design problems and bring provide a competitive specification very early in the design cycle. A working algorithm for the tool development is included in this report. / text

Orientador: Aílton Akira Shinoda / Resumo: Bastidores eletrônicos de alta performance e disponibilidade utilizam o protocolo Intelligent Platform Management Interface (IPMI) para gerenciar seus dispositivos, controlando e monitorando os recursos disponíveis. Neste contexto para inserir dispositivos com tecnologia mais avançada, novos projetos foram elaborados para atualização dos sistemas de hardware e software baseados em System-on-Chip (SoC), principalmente na área de Física de Alta Energia. Uma aplicação existente, desenvolvida na parceira São Paulo Research and Analysis Center – Fermi National Accelerator Laboratory (SPRACE–FERMILAB) na colaboração internacional do Compact Muon Solenoid detector/Large Hadron Collider/European Organization for Nuclear Research (CMS/LHC/CERN), utiliza o protocolo IPMI implementado em um microcontrolador, contudo, para o processo de atualização vigente, há um interesse desta implementação em SoC. Assim, esta pesquisa foi desenvolvida como o estudo da viabilidade da implementação IPMI em um SoC. Para estabelecer e verificar o protocolo IPMI via barramento I²C, a plataforma Xilinx ZC702 Evaluation Board foi utilizada com os respectivos dispositivos SoC Zynq e Erasable Programmable Memory (EEPROM). Além disso foi desenvolvido uma estrutura simples do IPMI no sistema operacional em tempo real (FreeRTOS) baseados em modelos de hardware e software criados na plataforma Xilinx IDE e SDK. Por meio dos resultados apresentados é possível constatar a viabilidade da implementação IPMI em sistema... (Resumo completo, clicar acesso eletrônico abaixo) / Abstract: High performance and availability electronic racks use the Intelligent Platform Management Interface (IPMI) protocol to manage your devices by controlling and monitoring available resources. In this context to insert devices with more advanced technology, new projects were elaborated to update the System-on-Chip (SoC) based hardware and software systems, mainly in the area of High Energy Physics. An existing application developed at the São Paulo Research and Analysis Center partner - Fermi National Accelerator Laboratory (SPRACE – FERMILAB) in the international collaboration of the Compact Muon Solenoid detector/Large Hadron Collider/European Organization for Nuclear Research (CMS/LHC/CERN) uses The IPMI protocol implemented in a microcontroller, however, for the current update process, there is an interest of this implementation in SoC. Thus, this research was developed as the study of the viability of implementing IPMI in a SoC. To establish and verify the IPMI protocol via I²C bus, the Xilinx ZC702 Evaluation Board platform was used with the respective SoC Zynq and Erasable Programmable Memory (EEPROM) devices. In addition, a simple IPMI framework in the real time operating system (FreeRTOS) based on hardware and software models created on the Xilinx IDE and SDK platform was developed. From the results presented, it is possible to verify the viability of IPMI implementation in systems such as SoC Zynq as platform management controller, which allows migration and further t... (Complete abstract click electronic access below) / Mestre

General propose processor (GPP) are demanded high performance in dataintensive applications, such as deep learning, high performance computation (HPC), where algorithm kernels like GEMM (general matrix-matrix multiply) and SPMV (sparse matrix-vector multiply) kernels are intensively used. The performance of these data-intensive applications are bounded with memory bandwidth, which is limited by computing & memory access coupling and memory wall effect. Recent works proposed streaming ISA extensions to maximum memory bandwidth, which decouple computation and memory access, prefetching data by memory access pattern, hiding architecture latency. However, the performance of irregular memory access still suffers from low bus utilization when transferring narrow stream elements on wide memory buses. To solve this problem, the project proposes a new on-chip bus protocol - AXI-PACK, extended from Advance eXtensible Interface4 (AXI4) on-chip protocol, which enables high bandwidth end-to-end irregular memory streaming. Next, an on-chip multi-banked SRAM memory system is designed for supporting AXI-PACK, and AXI-PACK is evaluated under an open-source RISC-V vector processor system. AXI-PACK demonstrates high bus utilization and bandwidth in irregular access, which helps speedup GEMM(element size = 32bits) kernel 6.1 times and SpMV(element size = 32bits) kernel 3.0 times under bus data width of 256 bits, comparing to standard AXI4 bus. / General propose processor (GPP) efterfrågas hög prestanda i dataintensiva applikationer, såsom djupinlärning, högpresterande beräkningar (HPC), där algoritmkärnor som GEMM (generell matris-matris multiplicera) och SPMV (sparse matrix-vector multiply) kärnor används intensivt. Prestandan för dessa dataintensiva applikationer är begränsade till minnesbandbredd, som begränsas av dator & minnesåtkomstkoppling och minnesväggeffekt. Nya arbeten föreslog strömning av ISA-förlängningar till maximal minnesbandbredd, som frikopplar beräkning och minnesåtkomst, förhämtning av data genom minnesåtkomstmönster, döljer arkitekturlatens. Emellertid lider prestandan för oregelbunden minnesåtkomst fortfarande av låg bussanvändning vid överföring av smala strömelement på breda minnesbussar. För att lösa detta problem föreslår projektet ett nytt on-chip-bussprotokoll - AXIPACK, utvidgat från Advance eXtensible Interface4 (AXI4) on-chip-protokoll, vilket möjliggör oregelbunden minnesströmning med hög bandbredd ändetill-ände. Därefter är ett SRAM-minnessystem med flera banker på chip designat för att stödja AXI-PACK, och AXI-PACK utvärderas under ett RISC-V vektorprocessorsystem med öppen källkod. AXI-PACK visar hög bussanvändning och bandbredd vid oregelbunden åtkomst, vilket hjälper till att snabba upp GEMM (elementstorlek = 32 bitar) kärnan 6,1 gånger och SpMV (elementstorlek = 32 bitar) kärnan 3,0 gånger under bussdatabredden på 256 bitar, jämfört med standard AXI4-buss .