Dispersed spectrum cognitive radio systems represent a promising approach to exploit the utilization of spectral resources to full extent. Therefore, the performance analysis of such systems is conducted in this research. The Average symbol error probability of dispersed spectrum cognitive radio systems is derived for two cases: where each channel realization experiences independent and dependent Nakagami-m fading, respectively. In addition, the derivation is extended to include the effects of modulation type and order by considering M-PSK and M-QAM modulation schemes. We then study the impacts of topology on the effective transport capacity performance of ad hoc dispersed spectrum cognitive radio systems where the nodes assume 3- dimensional (3D) configurations. We derive the effective transport capacity considering a cubic grid distribution. In addition, numerical results are presented to demonstrate the effects of topology on the effective transport capacity of ad hoc dispersed cognitive radio systems.

Orientador: Prof. Dr. Carlos Eduardo Capovilla / Dissertação (mestrado) - Universidade Federal do ABC, Programa de Pós-Graduação em Engenharia Elétrica, 2017. / Com a evolução dos meios de comunicação e a constante necessidade por altas taxas de transferencia de dados, a comunicação sem fio torna-se constantemente o principal e favorito meio para as mais diversas aplicações. Por aliar agilidade, desempenho e facilidade de instalação, é frequentemente encontrada em sistemas de controle, áudio e televisão, acesso a internet, etc. Porém, devido as imperfeições e ruído no canal, essa comunicação requer uma eficiente modulação e uma adequada proteção contra erros na transmissao dos dados. A versão IEEE 802.11g, presente em praticamente todos sistemas de comunicação moderno e amplamente difundido pelas redes conhecidas como WiFi surge como perfeita solução, pois permite alinhar técnicas robustas e efcientes, como a modulação OFDM e a codificação Convolucional. Alinhado ao conceito digital e a forma dinamica que a comunicação sem fio proporciona, o conceito de SDR (Software Dened Radio), torna-se uma interessante e poderosa ferramenta com a possibilidade de simulação e implementação de transceptores para diversas aplicaçõess em um único dispositivo. Assim, este projeto de mestrado tem como objetivo o estudo e testabilidade de um sistema IEEE 802.11g de comunicação sem fio utilizando dispositivo SDR, com foco em sistemas eficientes e de baixo custo, para fazer a interface entre o meio físico e o ambiente de processamento do sinal digital. / With the advancements of communication technology and the constant need for high rates of data transfer, wireless communication is consistently the main and favorite option for the most kind of applications. By combining agility, performance and fast installation, it is often found in control systems, audio and television systems, internet access, etc. However, due to the imperfections and noise in the channel, this communication requires an eficient modulation and an adequate protection against errors in the data transmission. The IEEE 802.11g standard, also used in practically all modern communication systems and widely difused by the networks known as WiFi, appears as a perfect solution, since it allows to align robust and eficient techniques such as OFDM modulation and Convolutional coding. Using digital concept and the dynamic behavior of wireless communication, the concept of SDR (Software Dened Radio) becomes an interesting and powerful tool because the possibility of simulation and implementation of transceivers for several applications in a single device. This project aims to make a wireless IEEE 802.11g communication system using Software Defined Radios focusing on low cost radios and high performance to make the interface between the real world and the digital signal processing.

Title from PDF of title page. / Document formatted into pages; contains 62 pages / Thesis (M.S.E.E.)--University of South Florida, 2003. / Includes bibliographical references. / Text (Electronic thesis) in PDF format. / ABSTRACT: The GSM platform is a extremely successful wireless technology and an unprecedented story of global achievement. The GSM platform is growing and evolving and offers an expanded and feature-rich voice and data enabling services. General Packet Radio Service, (GPRS), will have a tremendous transmission rate, which will make a significant impact on most of the existing services. Additionally, GPRS stands ready for the introduction of new services as operators and users, both business and private, appreciate the capabilities and potential that GPRS provides. Services such as the Internet, videoconferencing and on-line shopping will be as smooth as talking on the phone. Moreover, the capability and ease of access to these services increase at work, at home or during travel. In this research the traffic channel of a GSM system was studied in detail and simulated in order to obtain a performance analysis. Matlab, software from Mathworks, was used for the simulation. / ABSTRACT: Both the forward and the reverse links of a GSM system were simulated. A flat fading model was used to model the channel. Signal to Noise Ratio, (SNR), was the primary metric that was varied during the simulation. All the building blocks for a traffic channel, including a Convolutional encoder, an Interleaver and a Modulator were coded in Matlab. Finally the GPRS system, which is an enhancement of the GSM system for data services was introduced. / System requirements: World Wide Web browser and PDF reader. / Mode of access: World Wide Web.

This dissertation investigates the application of computational intelligence methods in the analysis of nonlinear chaotic systems in the framework of many known and newly designed complex systems. Parallel comparisons are made between these methods. This provides insight into the difficult challenges facing nonlinear systems characterization and aids in developing a generalized algorithm in computing algorithmic complexity measures, Lyapunov exponents, information dimension and topological entropy. These metrics are implemented to characterize the dynamic patterns of discrete and continuous systems. These metrics make it possible to distinguish order from disorder in these systems. Steps required for computing Lyapunov exponents with a reorthonormalization method and a group theory approach are formalized. Procedures for implementing computational algorithms are designed and numerical results for each system are presented. The advance-time sampling technique is designed to overcome the scarcity of phase space samples and the buffer overflow problem in algorithmic complexity measure estimation in slow dynamics feedback-controlled systems. It is proved analytically and tested numerically that for a quasiperiodic system like a Fibonacci map, complexity grows logarithmically with the evolutionary length of the data block. It is concluded that a normalized algorithmic complexity measure can be used as a system classifier. This quantity turns out to be one for random sequences and a non-zero value less than one for chaotic sequences. For periodic and quasi-periodic responses, as data strings grow their normalized complexity approaches zero, while a faster deceasing rate is observed for periodic responses. Algorithmic complexity analysis is performed on a class of certain rate convolutional encoders. The degree of diffusion in random-like patterns is measured. Simulation evidence indicates that algorithmic complexity associated with a particular class of 1/n-rate code increases with the increase of the encoder constraint length. This occurs in parallel with the increase of error correcting capacity of the decoder. Comparing groups of rate-1/n convolutional encoders, it is observed that as the encoder rate decreases from 1/2 to 1/7, the encoded data sequence manifests smaller algorithmic complexity with a larger free distance value.

To achieve the goal of efficient ”anytime, anywhere” communication, it is essential to develop mobile devices which can efficiently support multiple wireless communication standards. Also, in order to efficiently accommodate the further evolution of these standards, it should be possible to modify/upgrade the operation of the mobile devices without having to recall previously deployed devices. This is achievable if as much functionality of the mobile device as possible is provided through software. A mobile device which fits this description is called a Software Defined Radio (SDR). Reconfigurable hardware-based solutions are an attractive option for realizing SDRs as they can potentially provide a favourable combination of the flexibility of a DSP or a GPP and the efficiency of an ASIC. The work presented in this thesis discusses the development of efficient reconfigurable hardware for one of the most energy-intensive functionalities in the mobile device, namely, Forward Error Correction (FEC). FEC is required in order to achieve reliable transfer of information at minimal transmit power levels. FEC is achieved by encoding the information in a process called channel coding. Previous studies have shown that the FEC unit accounts for around 40% of the total energy consumption of the mobile unit. In addition, modern wireless standards also place the additional requirement of flexibility on the FEC unit. Thus, the FEC unit of the mobile device represents a considerable amount of computing ability that needs to be accommodated into a very small power, area and energy budget. Two channel coding techniques have found widespread use in most modern wireless standards -namely convolutional coding and turbo coding. The Viterbi algorithm is most widely used for decoding convolutionally encoded sequences. It is possible to use this algorithm iteratively in order to decode turbo codes. Hence, this thesis specifically focusses on developing architectures for flexible Viterbi decoders. Chapter 2 provides a description of the Viterbi and turbo decoding techniques. The flexibility requirements placed on the Viterbi decoder by modern standards can be divided into two types -code rate flexibility and constraint length flexibility. The code rate dictates the number of received bits which are handled together as a symbol at the receiver. Hence, code rate flexibility needs to be built into the basic computing units which are used to implement the Viterbi algorithm. The constraint length dictates the number of computations required per received symbol as well as the manner of transfer of results between these computations. Hence, assuming that multiple processing units are used to perform the required computations, supporting constraint length flexibility necessitates changes in the interconnection network connecting the computing units. A constraint length K Viterbi decoder needs 2K−1computations to be performed per received symbol. The results of the computations are exchanged among the computing units in order to prepare for the next received symbol. The communication pattern according to which these results are exchanged forms a graph called a de Bruijn graph, with 2K−1nodes. This implies that providing constraint length flexibility requires being able to realize de Bruijn graphs of various sizes on the interconnection network connecting the processing units. This thesis focusses on providing constraint length flexibility in an efficient manner. Quite clearly, the topology employed for interconnecting the processing units has a huge effect on the efficiency with which multiple constraint lengths can be supported. This thesis aims to explore the usefulness of interconnection topologies similar to the de Bruijn graph, for building constraint length flexible Viterbi decoders. Five different topologies have been considered in this thesis, which can be discussed under two different headings, as done below: De Bruijn network-based architectures The interconnection network that is of chief interest in this thesis is the de Bruijn interconnection network itself, as it is identical to the communication pattern for a Viterbi decoder of a given constraint length. The problem of realizing flexible constraint length Viterbi decoders using a de Bruijn network has been approached in two different ways. The first is an embedding-theoretic approach where the problem of supporting multiple constraint lengths on a de Bruijn network is seen as a problem of embedding smaller sized de Bruijn graphs on a larger de Bruijn graph. Mathematical manipulations are presented to show that this embedding can generally be accomplished with a maximum dilation of, where N is the number of computing nodes in the physical network, while simultaneously avoiding any congestion of the physical links. In this case, however, the mapping of the decoder states onto the processing nodes is assumed fixed. Another scheme is derived based on a variable assignment of decoder states onto computing nodes, which turns out to be more efficient than the embedding-based approach. For this scheme, the maximum number of cycles per stage is found to be limited to 2 irrespective of the maximum contraint length to be supported. In addition, it is also found to be possible to execute multiple smaller decoders in parallel on the physical network, for smaller constraint lengths. Consequently, post logic-synthesis, this architecture is found to be more area-efficient than the architecture based on the embedding theoretic approach. It is also a more efficiently scalable architecture. Alternative architectures There are several interconnection topologies which are closely connected to the de Bruijn graph, and hence could form attractive alternatives for realizing flexbile constraint length Viterbi decoders. We consider two more topologies from this class -namely, the shuffle-exchange network and the flattened butterfly network. The variable state assignment scheme developed for the de Bruijn network is found to be directly applicable to the shuffle-exchange network. The average number of clock cycles per stage is found to be limited to 4 in this case. This is again independent of the constraint length to be supported. On the flattened butterfly (which is actually identical to the hypercube), a state scheduling scheme similar to that of bitonic sorting is used. This architecture is found to offer the ideal throughput of one decoded bit every clock cycle, for any constraint length. For comparison with a more general purpose topology, we consider a flexible constraint length Viterbi decoder architecture based on a 2D-mesh, which is a popular choice for general purpose applications, as well as many signal processing applications. The state scheduling scheme used here is also similar to that used for bitonic sorting on a mesh. All the alternative architectures are capable of executing multiple smaller decoders in parallel on the larger interconnection network. Inferences Following logic synthesis and power estimation, it is found that the de Bruijn network-based architecture with the variable state assignment scheme yields the lowest (area)−(time) product, while the flattened butterfly network-based architecture yields the lowest (area) - (time)2product. This means, that the de Bruijn network-based architecture is the best choice for moderate throughput applications, while the flattened butterfly network-based architecture is the best choice for high throughput applications. However, as the flattened butterfly network is less scalable in terms of size compared to the de Bruijn network, it can be concluded that among the architectures considered in this thesis, the de Bruijn network-based architecture with the variable state assignment scheme is overall an attractive choice for realizing flexible constraint length Viterbi decoders.

Channel coding has been largely used for the purpose of improving error performance on a communications system. Typical methods based on added redundancy allow for error detection and correction, this improvement however comes at a cost of bandwidth. This thesis focuses on channel coding for the bandwidth-limited channel where no bandwidth expansion is allowed. We first discuss the idea of coding for the bandwidth-limited channel as seen from the signal space point of view where the purpose of coding is to maximize the Euclidian distance between constellation points without increasing the total signal power and under the condition that no extra bits can be added. We then see the problem from another angle and identify the tradeoffs related to bandwidth and error performance. This thesis intends to find a simple way of achieving an improvement in error performance for the bandwidth-limited channel without the use of lattice codes or trellis-coded modulation. The proposed system is based on convolutional coding followed by multilevel transmission. It achieved a coding gain of 2 dB on Eb/No or equivalently, a coding gain of approximately 2.7 dB on SNRnorm without increase in bandwidth. This coding gain is better than that obtained by a more sophisticated lattice code Gosset E8 at the same error rate.

Frame synchronization is an important problem in digital communication systems. In frame synchronization, the main task is to find the frame start given the flow of the communication symbols. In this thesis, frame synchronization problem is investigated for both additive white Gaussian noise (AWGN) channels and frequency selective channels. Most of the previous works on frame synchronization consider the simple case of AWGN channels. The algorithms developed for this purpose fail in frequency selective channels. There is limited number of algorithms proposed for the frequency selective channels. In this thesis, existing frame synchronization techniques are investigated for both AWGN and frequency selective channels. Code-aided frame synchronization techniques are combined with the methods for frequency selective channels. Mainly two types of code-aided frame synchronization schemes are considered and two new system structures are proposed for frame synchronization. One of the proposed structures performs better than the alternative methods for frequency selective channels. The overall system for this new synchronizer is composed of a list synchronizer which generates the possible frame starts, a channel estimator, a soft output MLSE equalizer, and a soft output Viterbi decoder. A mode separation algorithm is used to generate the statistics for the selection of the true frame start. Several experiments are done and the performance is outlined for a variety of scenarios.

Approved for public release; distribution is unlimited / OFDM systems have experienced increased attention in recent years and have found applications in a number of diverse areas including telephone-line based ADSL links, digital audio and video broadcasting systems, and wireless local area networks (WLAN). Orthogonal frequency-division multiplexing (OFDM) is a powerful technique for high data-rate transmission over fading channels. However, to deploy OFDM in a WLAN environment, precise frequency synchronization must be maintained and tricky frequency offsets must be handled. In this thesis, various techniques to improve the data throughput of OFDM WLAN are investigated. A simulation tool was developed in Matlab to evaluate the performance of the IEEE 802.11a physical layer. We proposed a rapid time and frequency synchronization algorithm using only the short training sequence of the IEEE 802.11a standard, thus reducing the training overhead to 50%. Particular attention was paid to channel coding, block interleaving and antenna diversity. Computer simulation showed that drastic improvement in error rate performance is achievable when these techniques are deployed. / Lieutenant, Hellenic Navy