ITC/USA 2008 Conference Proceedings / The Forty-Fourth Annual International Telemetering Conference and Technical Exhibition / October 27-30, 2008 / Town and Country Resort & Convention Center, San Diego, California / A critical element of the proposed iNET architecture is the development of a telemetry network that provides two-way communication between multiple nodes on both the ground and in the air. Conventional airborne telemetry is based on IRIG-106 Chapter 4 and provides only a serial streaming data path from the aircraft to the ground. The network-centric architecture of iNET requires not only a duplex communication link between the ground and the test article, but also a communication link that provides higher bandwidth performance, higher spectrum efficiency, and a transport environment that is capable of fully packetized Internet Protocol. This paper describes the development path followed by TTC in the implementation of its nXCVR-2000G, an OFDM 802-11a-based iNET-ready IP transceiver.

The IEEE 802.11a has become the mainstream protocol used in modern wireless communication system due to its high propagation rate of data (54 Mb/s). To meet high propagation rates, the communication devices used in IEEE 802.11a protocol usually present a high conversion gain and a high linearity (denoted as third order intercept point, IIP3). The IIP3 of conventional up- and down-conversion mixers are only about 0 dBm and -5 dBm, which fail to achieve a high propagation rate of data. This thesis utilizes the TSMC 0.18 µm CMOS technology to design and fabrication up- and down-conversion mixers with very high linearity for IEEE 802.11a application. The proposed high-linearity up-conversion mixer with 1.01 mm ¡Ñ 0.85 mm chip size and its wide bandwidth (5~6 GHz) is well suited for IEEE 802.11a application. To enhance the linearity and bandwidth, a transconductor stage with gm-boosted structure, a switch stgae with LO-body grounded structure and a load stage with shunt peaking structure are adopted in this research. Under 5.2/5.4/5.8 GHz operating frequencies, the implemented up-conversion mixer demonstrates a high conversion gain of 6.8/7.1/6.3 dB and a high linearity of 8.9/9/13.2 dBm, respectivly. In addition, a moderate consuming power (6.86 mW) of such mixer can be achieved at 1.2 V supply voltage. On the other hand, this thesis also designed and fabricated a high-linearity down-conversion mixer with chip size of 1.02 mm ¡Ñ 0.86 mm and 5.2 GHz center frequency. To improve the linearity and isolation and reduce the high-order noise, a transconductor stage with dual-gate structure and a load stage with RC-tank structure are adopted in this research. According to the EM-simulation resutls, the proposed down-conversion mixer presents a moderate conversion gain of 6 dB and a high linearity of 0.8 dBm. Additionly, a moderate consuming power (6.75 mW) of such mixer can be achieved at 1.8 V supply voltage.

The IEEE 802.11a has become the mainstream protocol used in modern wireless communication system due to its high propagation rate of data (54 Mb/s). To meet high propagation rates, the communication devices used in IEEE 802.11a protocol usually present a high conversion gain and a high linearity (denoted as third order intercept point, IIP3). The IIP3 of conventional up- and down-conversion mixers are only about 0 dBm and -5 dBm, which fail to achieve a high propagation rate of data. This thesis utilizes the TSMC 0.18 £gm CMOS technology to design and fabrication up- and down-conversion mixers with very high linearity for IEEE 802.11a application. The proposed high-linearity up-conversion mixer with 1.01 mm ¡Ñ 0.85 mm chip size and its wide bandwidth (5~6 GHz) is well suited for IEEE 802.11a application. To enhance the linearity and bandwidth, a transconductor stage with gm-boosted structure, a switch stgae with LO-body grounded structure and a load stage with shunt peaking structure are adopted in this research. Under 5.2/5.4/5.8 GHz operating frequencies, the implemented up-conversion mixer demonstrates a high conversion gain of 6.8/7.1/6.3 dB and a high linearity of 8.9/9/13.2 dBm, respectivly. In addition, a moderate consuming power (6.86 mW) of such mixer can be achieved at 1.2 V supply voltage. On the other hand, this thesis also designed and fabricated a high-linearity down-conversion mixer with chip size of 1.02 mm ¡Ñ 0.86 mm and 5.2 GHz center frequency. To improve the linearity and isolation and reduce the high-order noise, a transconductor stage with dual-gate structure and a load stage with RC-tank structure are adopted in this research. According to the EM-simulation resutls, the proposed down-conversion mixer presents a moderate conversion gain of 6 dB and a high linearity of 0.8 dBm. Additionly, a moderate consuming power (6.75 mW) of such mixer can be achieved at 1.8 V supply voltage.

ABSTRACT In the past decade there has been a steady growth in development and implementation of wireless Local Area Networks and emerged as in the largest sectors of the telecommunication industry. Wireless local area network (WLANs) provides connectivity, mobility, and much higher performance and achievable data rate. WLAN is a new medium of access technology in the Local Area Network (LAN) world. Mostly WLAN applications are used in public sectors such as airports, banks, hotels, offices, city centres because of the flexibility of the people. Orthongonal Frequency Division Multiplexing OFDM has been adopted by IEEE 802.11’s standard as a transmission technique for high data rate in WLANs. Now IEEE 802.11 standard has been expanded to a family of WLAN standards. 802.11a and 802.11g both are used Orthongonal Frequency Division Multiplexing (OFDM) but operate in different frequency bands. It is shown that 802.11a provides high speed throughout the entire coverage area and long term solution however it does not provide better solution in most cases as compared to IEEE 802.11g. Matlab Simulation model based on IEEE 802.11a/g using different modulation and demodulation techniques such as BPSK, QPSK and QAM to analysis the best performance of IEEE 802.11a/g with implementation of OFDM. Keywords: Orthongonal Frequency Division Multiplexing (OFDM), IEEE 802.11s family, Wireless Local Area Network, Simulation, MATLAB / Summary The objective of this research is to examine the performance of the IEEE 802.11a and IEEE 802.11g WLAN comparing through OFDM modulation techniques. It is found that IEEE 802.11a/g provides similar quality except IEEE 802.11g provides wider range but range is the controversial topic in WLAN medium. In the other hand IEEE 802.11a provides more channels in 5 GHz bands as well as have a good enough signal qualities but there is range limitation factor. Range limitation in the enterprise and public sectors can be adjusting through installations more APs. The main disadvantage of the 802.11g is the frequency band is common and interference from the other networking technology such as Bluetooth, 2.04 GHz cordless phone and IEEE 802.11a avoid this interference because its operate in 5.GHz bands. Consequently, all the simulation is a comparison between simulated BER for a computer system and theoretical BER for serial systems it has been proved through simulation results that theoretical BER and simulated BER under AWGN are good agreement with each other. It means that I and Q points on constellation are much closer to each other the data error can be reduced as well as transmission easily influenced to noise. 64 QAM modulations are much better than 16 QAM when BER decrease SNR will be increase because signal is stronger than noise. 64 QAM modulations need higher bandwidth and give an excellent data rates as compared to 16 QAM.

Approved for public release, distribution is unlimited / As the need to send larger amounts of information increases, the military is looking into viable solutions to push this information throughout the battle space. IEEE 802.11a wireless LAN network presents an attractive high-speed solution by providing data rates up to 54 Mbps. At the same time, wireless LAN introduces increased security risk due to its vulnerability to exploitation of the wireless LAN physical layer. This research will develop a prototype system using low cost hardware and software solution to detect and process wireless IEEE 802.11a signals. Using the prototype, performance data will be collected to determine whether IEEE 802.11a is a feasible option as a high-speed information network for military use. Additionally, the performance data collected will provide a good basis for predicting the expected performance in an operational scenario and provide valuable information for proper deployment planning. / Major, Republic of Singapore Air Force

In a typical orthogonal frequency division multiplexing (OFDM) broadband wireless communication system, a guard interval using cyclic prefix is inserted to avoid the inter-symbol interference and the inter-carrier interference. This guard interval is required to be at least equal to, or longer than the maximum channel delay spread. This method is very simple, but it reduces the transmission efficiency. This efficiency is very low in the communication systems, which inhibit a long channel delay spread with a small number of sub-carriers such as the IEEE 802.11a wireless LAN (WLAN). To increase the transmission efficiency, it is usual that a time domain equalizer (TEQ) is included in an OFDM system to shorten the effective channel impulse response within the guard interval. There are many TEQ algorithms developed for the low rate OFDM applications such as asymmetrical digital subscriber line (ADSL). The drawback of these algorithms is a high computational load. Most of the popular TEQ algorithms are not suitable for the IEEE 802.11a system, a high data rate wireless LAN based on the OFDM technique. In this thesis, a TEQ algorithm based on the minimum mean square error criterion is investigated for the high rate IEEE 802.11a system. This algorithm has a comparatively reduced computational complexity for practical use in the high data rate OFDM systems. In forming the model to design the TEQ, a reduced convolution matrix is exploited to lower the computational complexity. Mathematical analysis and simulation results are provided to show the validity and the advantages of the algorithm. In particular, it is shown that a high performance gain at a data rate of 54Mbps can be obtained with a moderate order of TEQ finite impulse response (FIR) filter. The algorithm is implemented in a field programmable gate array (FPGA). The characteristics and regularities between the elements in matrices are further exploited to reduce the hardware complexity in the matrix multiplication implementation. The optimum TEQ coefficients can be found in less than 4µs for the 7th order of the TEQ FIR filter. This time is the interval of an OFDM symbol in the IEEE 802.11a system. To compensate for the effective channel impulse response, a function block of 64-point radix-4 pipeline fast Fourier transform is implemented in FPGA to perform zero forcing equalization in frequency domain. The offsets between the hardware implementations and the mathematical calculations are provided and analyzed. The system performance loss introduced by the hardware implementation is also tested. Hardware implementation output and simulation results verify that the chips function properly and satisfy the requirements of the system running at a data rate of 54 Mbps.

In a typical orthogonal frequency division multiplexing (OFDM) broadband wireless communication system, a guard interval using cyclic prefix is inserted to avoid the inter-symbol interference and the inter-carrier interference. This guard interval is required to be at least equal to, or longer than the maximum channel delay spread. This method is very simple, but it reduces the transmission efficiency. This efficiency is very low in the communication systems, which inhibit a long channel delay spread with a small number of sub-carriers such as the IEEE 802.11a wireless LAN (WLAN). To increase the transmission efficiency, it is usual that a time domain equalizer (TEQ) is included in an OFDM system to shorten the effective channel impulse response within the guard interval. There are many TEQ algorithms developed for the low rate OFDM applications such as asymmetrical digital subscriber line (ADSL). The drawback of these algorithms is a high computational load. Most of the popular TEQ algorithms are not suitable for the IEEE 802.11a system, a high data rate wireless LAN based on the OFDM technique. In this thesis, a TEQ algorithm based on the minimum mean square error criterion is investigated for the high rate IEEE 802.11a system. This algorithm has a comparatively reduced computational complexity for practical use in the high data rate OFDM systems. In forming the model to design the TEQ, a reduced convolution matrix is exploited to lower the computational complexity. Mathematical analysis and simulation results are provided to show the validity and the advantages of the algorithm. In particular, it is shown that a high performance gain at a data rate of 54Mbps can be obtained with a moderate order of TEQ finite impulse response (FIR) filter. The algorithm is implemented in a field programmable gate array (FPGA). The characteristics and regularities between the elements in matrices are further exploited to reduce the hardware complexity in the matrix multiplication implementation. The optimum TEQ coefficients can be found in less than 4µs for the 7th order of the TEQ FIR filter. This time is the interval of an OFDM symbol in the IEEE 802.11a system. To compensate for the effective channel impulse response, a function block of 64-point radix-4 pipeline fast Fourier transform is implemented in FPGA to perform zero forcing equalization in frequency domain. The offsets between the hardware implementations and the mathematical calculations are provided and analyzed. The system performance loss introduced by the hardware implementation is also tested. Hardware implementation output and simulation results verify that the chips function properly and satisfy the requirements of the system running at a data rate of 54 Mbps.

Kraven på dagens trådlösa förbindelser kommer hela tiden att öka och med detta följer även högre krav på nya produkter som kan tillgodose de ökade kraven. För att göra processen från idé till produkt snabbare krävs enkla verktyg för att snabbt kunna gå från den formulerade standarden till en hårdvaruprototyp. Detta arbete har använt sig av ett av dessa verktyg som idag finns tillgängliga, Xilinx System Generator for DSP 1.1, för att ta fram sändare och mottagare för en del av den trådlösa standarden IEEE 802.11a. Arbetet ger en beskrivning av hur sändare och mottagare är uppbyggda samt även synpunkter på System Generator och beskrivningar av problem som uppstod under arbetet. / The demands on todays wireless communications will continue to increase and with this follows a demand for shorter and shorter development times for the products that are going to satisfy this demand. To accomplish this shorter development time simple tools for going from the formulated standard to a hardware prototype is needed. This work uses one of these tools today available, Xilinx System Generator for DSP 1.1, to develop a transmitter and a reciever for a part of the wireless standard IEEE 802.11a. The work gives a description of the building blocks of the transmitter and the reciever but also some views on System Generator and descriptions of problems that were encountered during the work.

In the high-speed indoor wireless applications, IEEE 802.11 series is the most dominating LAN standard in the current markets. In this thesis, the design issues of the IEEE 802.11a physical layer baseband system are addressed. Various key modules including Viterbi codec, FFT/IFFT module, OFDM synchronous circuit have been integrated with several other modules to constitute the entire baseband system. This system has been implemented by Verilog HDL and verified against with the C-based behavior model. In addition, it will also be prototyped and optimized on the Altera DSP FPGA Development Board. The transmission of the I, Q channel for the time domain singal is emulated by using the 10-bits AD/DA modules on the FPGA board. The experimental results shows that the gate counts of the transmitter and the receiver are 81,190 and 413,461 respectively.

<p>Kraven på dagens trådlösa förbindelser kommer hela tiden att öka och med detta följer även högre krav på nya produkter som kan tillgodose de ökade kraven. För att göra processen från idé till produkt snabbare krävs enkla verktyg för att snabbt kunna gå från den formulerade standarden till en hårdvaruprototyp. Detta arbete har använt sig av ett av dessa verktyg som idag finns tillgängliga, Xilinx System Generator for DSP 1.1, för att ta fram sändare och mottagare för en del av den trådlösa standarden IEEE 802.11a. Arbetet ger en beskrivning av hur sändare och mottagare är uppbyggda samt även synpunkter på System Generator och beskrivningar av problem som uppstod under arbetet. </p> / <p>The demands on todays wireless communications will continue to increase and with this follows a demand for shorter and shorter development times for the products that are going to satisfy this demand. To accomplish this shorter development time simple tools for going from the formulated standard to a hardware prototype is needed. This work uses one of these tools today available, Xilinx System Generator for DSP 1.1, to develop a transmitter and a reciever for a part of the wireless standard IEEE 802.11a. The work gives a description of the building blocks of the transmitter and the reciever but also some views on System Generator and descriptions of problems that were encountered during the work.</p>