Aνάπτυξη αποδοτικών αρχιτεκτονικών για την υλοποίηση του (FFT/IFFT) για εφαρμογές ασυρμάτων τοπικών δικτύων. Ανάπτυξη Αρχιτεκτονικών υψηλής παραμετροποιήσης ως πρός διαφορετικούς παράγοντες όπως το μέγεθος του μετασχηματισμού, τα εύρη σε αριθμό δυαδικών ψηφίων των εισόδων, των εξόδων και των συντελεστών. Βελτιστοποίηση άλλων βασικών παραγόντων κόστους υλοποίησης όπως η επιφάνεια και η ισχύς. / Sufficient development for the FFT/iFFT implementation in Wireless Local Networks (wLANs). Specific architectural development was established in order to achieve constraints in different factors such as the size of the transform or the dual input-output digits´ width. Improvement in basic factors was also achieved, in order to gain low cost implementation in sueface and power.

Made available in DSpace on 2016-03-15T19:37:47Z (GMT). No. of bitstreams: 1 Luiz Carlos Bernardo.pdf: 7288586 bytes, checksum: b7562f834db8a5ce808707075e7ce04b (MD5) Previous issue date: 2013-06-14 / A chaotic signal based communication system represents a new wideband transmission model. Nonetheless, chaotic based systems have not yet shown a distinguished performance in terms of bit error rate when transmitted in narrow band channels or in the presence of impairments in comparison to the traditional communications systems. The focus of this work relies on an experiment that overcomes this issue, through the conjugation of the characteristics of traditional communications based in orthogonal carriers and those originated from chaotic signals. More clearly, the chaotic modulation is employed in sub-carriers of traditional OFDM (Orthogonal Frequency Division Multiplexing). This novel modulation scheme is implemented through the generation of chaotic sequences in a one dimensional map controlled by a parameter p which defines the central region of the map as a guard interval, the slope of the delimiting lines and the chaotic behavior of the generated sequence. This parameter also determines directly the amplitude of each symbol, making it more irregular and less predictable, avoiding the detection by eavesdroppers and increasing the security level of the link to be transmitted. Besides the change in the traditional OFDM modulator from 4QAM to chaotic one, the Fast Fourier Transform (IFFT /FFT) will be replaced by Wavelets Transform IDWT/DWT), in order to overcome some conventional OFDM s disadvantages Additionally a quadrature chaotic OFDM system was conceived, where the chaotic modulation was performed in a constellation I and Q that was submitted to the same channel conditions as the previous one. Both systems were simulated in a MATLAB® environment using the built in functions at the Communications System Toolbox and its behavior analyzed using the BER-Bit error rate versus SNR-Signal noise ratio. The obtained results were reported and scrutinized. / Sistemas de comunicações baseados em sinais caóticos representam um novo campo de estudo de transmissão em banda larga. Entretanto, sistemas baseados em sinais caóticos não apresentaram ainda um desempenho distinto em termos de taxa de erro, quando transmitidos em canais sem fios ou na presença de interferências em comparação aos sistemas tradicionais. O foco deste trabalho está na proposta de um novo esquema obtido através da conjugação das características da comunicação tradicional baseada em subportadoras ortogonais e aquelas originadas por sinais caóticos. Mais precisamente, a modulação caótica é empregada nas subportadoras de um sistema OFDM (Multiplexação por Divisão de Frequência Ortogonal) tradicional. Este novo modelo de modulação é implementado através de geração de sequências caóticas em um mapa unidimensional controlado por um parâmetro p que define uma região central do mapa como um intervalo de guarda e, por conseguinte, o comportamento caótico da sequência gerada. Este parâmetro também determina diretamente a amplitude de cada símbolo, fazendo-o mais irregular e menos previsível, evitando a detecção por pessoal não autorizado, possibilitando o aumento do nível de segurança da transmissão. Além da mudança no modulador do OFDM convencional de 4QAM para caótico, ter-se-á a substituição da Transformada Rápida de Fourier (IFFT/FFT), largamente utilizada em sistemas OFDM pela Transformada Wavelet (IDWT/DWT), de maneira a aprimorar os pontos fracos do sistema OFDM convencional. Como contribuição adicional, tem se a concepção do sinal com modulação simbólica em quadratura, ou seja, uma parte do sinal foi gerada no eixo I e a outra parte no eixo Q, criando uma modulação caótica em quadratura que é submetida aos mesmos canais da modulação caótica anterior. Os sistemas propostos foram simulados em ambiente MATLAB® utilizando-se de funções pré-existentes no modulo de ferramentas de comunicações (Communications System Toolbox) e o seu comportamento analisado em termos de gráficos que representam a relação da taxa de erro do bit (BER) versus relação sinal ruído (SNR). Os resultados obtidos foram reportados e debatidos.

<p><p>Benchmarking of DSP kernel algorithms was conducted in the thesis on a DSP processor for teaching in the course TESA26 in the department of Electrical Engineering. It includes benchmarking on cycle count and memory usage. The goal of the thesis is to evaluate the quality of a single MAC DSP instruction set and provide suggestions for further improvement in instruction set architecture accordingly. The scope of the thesis is limited to benchmark the processor only based on assembly coding. The quality check of compiler is not included. The method of the benchmarking was proposed by BDTI, Berkeley Design Technology Incorporations, which is the general methodology used in world wide DSP industry.</p><p>Proposals on assembly instruction set improvements include the enhancement of FFT and DCT. The cycle cost of the new FFT benchmark based on the proposal was XX% lower, showing that the proposal was right and qualified. Results also show that the proposal promotes the cycle cost score for matrix computing, especially matrix multiplication. The benchmark results were compared with general scores of single MAC DSP processors offered by BDTI.</p></p>

<p>3GPP LTE (Long Term Evolution) is a project of the Third Generation Partnership Project to improve the UMTS (Universal Mobile Telecommunications System) mobile phone standard to cope with future technology evolutions. Two duplex schemes FDD and TDD are investigated in this thesis. Several computational intensive components of the baseband processing for LTE uplink such as synchronization, channel estimation, equalization, soft demapping, turbo decoding is analyzed. Cost analysis is hardware independent so that only computational complexity is considered in this thesis. Hardware dependent discussion for LTE baseband SDR platform is given according the analysis results.</p>

Benchmarking of DSP kernel algorithms was conducted in the thesis on a DSP processor for teaching in the course TESA26 in the department of Electrical Engineering. It includes benchmarking on cycle count and memory usage. The goal of the thesis is to evaluate the quality of a single MAC DSP instruction set and provide suggestions for further improvement in instruction set architecture accordingly. The scope of the thesis is limited to benchmark the processor only based on assembly coding. The quality check of compiler is not included. The method of the benchmarking was proposed by BDTI, Berkeley Design Technology Incorporations, which is the general methodology used in world wide DSP industry. Proposals on assembly instruction set improvements include the enhancement of FFT and DCT. The cycle cost of the new FFT benchmark based on the proposal was XX% lower, showing that the proposal was right and qualified. Results also show that the proposal promotes the cycle cost score for matrix computing, especially matrix multiplication. The benchmark results were compared with general scores of single MAC DSP processors offered by BDTI.

Kraven på dagens trådlösa förbindelser kommer hela tiden att öka och med detta följer även högre krav på nya produkter som kan tillgodose de ökade kraven. För att göra processen från idé till produkt snabbare krävs enkla verktyg för att snabbt kunna gå från den formulerade standarden till en hårdvaruprototyp. Detta arbete har använt sig av ett av dessa verktyg som idag finns tillgängliga, Xilinx System Generator for DSP 1.1, för att ta fram sändare och mottagare för en del av den trådlösa standarden IEEE 802.11a. Arbetet ger en beskrivning av hur sändare och mottagare är uppbyggda samt även synpunkter på System Generator och beskrivningar av problem som uppstod under arbetet. / The demands on todays wireless communications will continue to increase and with this follows a demand for shorter and shorter development times for the products that are going to satisfy this demand. To accomplish this shorter development time simple tools for going from the formulated standard to a hardware prototype is needed. This work uses one of these tools today available, Xilinx System Generator for DSP 1.1, to develop a transmitter and a reciever for a part of the wireless standard IEEE 802.11a. The work gives a description of the building blocks of the transmitter and the reciever but also some views on System Generator and descriptions of problems that were encountered during the work.

<p>Kraven på dagens trådlösa förbindelser kommer hela tiden att öka och med detta följer även högre krav på nya produkter som kan tillgodose de ökade kraven. För att göra processen från idé till produkt snabbare krävs enkla verktyg för att snabbt kunna gå från den formulerade standarden till en hårdvaruprototyp. Detta arbete har använt sig av ett av dessa verktyg som idag finns tillgängliga, Xilinx System Generator for DSP 1.1, för att ta fram sändare och mottagare för en del av den trådlösa standarden IEEE 802.11a. Arbetet ger en beskrivning av hur sändare och mottagare är uppbyggda samt även synpunkter på System Generator och beskrivningar av problem som uppstod under arbetet. </p> / <p>The demands on todays wireless communications will continue to increase and with this follows a demand for shorter and shorter development times for the products that are going to satisfy this demand. To accomplish this shorter development time simple tools for going from the formulated standard to a hardware prototype is needed. This work uses one of these tools today available, Xilinx System Generator for DSP 1.1, to develop a transmitter and a reciever for a part of the wireless standard IEEE 802.11a. The work gives a description of the building blocks of the transmitter and the reciever but also some views on System Generator and descriptions of problems that were encountered during the work.</p>

3GPP LTE (Long Term Evolution) is a project of the Third Generation Partnership Project to improve the UMTS (Universal Mobile Telecommunications System) mobile phone standard to cope with future technology evolutions. Two duplex schemes FDD and TDD are investigated in this thesis. Several computational intensive components of the baseband processing for LTE uplink such as synchronization, channel estimation, equalization, soft demapping, turbo decoding is analyzed. Cost analysis is hardware independent so that only computational complexity is considered in this thesis. Hardware dependent discussion for LTE baseband SDR platform is given according the analysis results.

<p>DVB (Digital Video Broadcasting) is the television digital system. It's however much more than a simple replacement for existing analogue television transmission, this system has many advantages such as picture quality and allows you a range of new features and services including subtitling, multiple audio tracks, interactive content, multimedia content. </p><p>The system is based in the OFDM technology, which allows DVB system to exploit the spectrum frequencies in a better way, saving spectrum, but OFDM has an important drawback that is the peak to average power ratio problem. OFDM is based on the FFT algorithms generating orthogonal subcarriers. </p><p>This thesis talks about the improvement of the PAPR problem using the soft compression method. </p><p>The simulation has been developed in Simulink® and Matlab®. With all the information presented in this thesis, any user can simulate the system. Thus, this thesis can be improved using other techniques to solve the PAPR problem.</p>

In digital communication systems, satellites give us world wide services. These satellites should effectively use the available bounded frequency spectrum and, therefore, to carry out flexible frequency-band reallocation (FFBR), on-board signal processing implementation on FFBR network is needed. In the future, to design desired dynamic communication systems, very flexible digital signal processing structures will be needed. The hardware, in the system, shall not be changed as simple changes in the software will be made. The purpose of this thesis is to implement an N-channel FFBR network, where N=20. A 20-channel FFBR network consists of different blocks, e.g., DFT, IDFT, complex multipliers, input/output commutators and polyphase components. The whole 20-channel FFBR network will be implemented in VHDL. In a 20-channel FFBR network, it is a 20-point FFT/IFFT required. This 20-point FFT/IFFT is built by a combination of radix-4 and radix-5 butterflies. The Cooley-Tukey FFT algorithm is chosen to build the 20-point FFT/IFFT. The main aim is to build 20-point FFT/IFFT. There are 20 complex multipliers before the IFFT block and 20 complex multipliers after the IFFT block. In the same way, 20 complex multipliers are used before the FFT block and 20 complex multipliers are used after the FFT block. At the input/output to this FFBR network, 20 FIR filters (polyphase components) are used, respectively.