This thesis focuses on a user-friendly software-defined radio (SDR) development workflow for prototyping, research and education in wireless communications and networks. Specifically, a Simulink interface to the Universal Software Radio Peripheral 2(USRP2) SDR platform is devised in order to enable over-the-air data transmission and reception using a Simulink signal source and sink, in addition to controlling a subset of the hardware resources of the USRP2 platform. Using the USRP2 as the RF front end, this interface will use Simulink for software radio development and signal processing libraries of the digital baseband component of the communication transceiver design. This combination of hardware and software will enable the rapid design, implementation, and verification of digital communications systems in simulation, while allowing the user to easily test the system with near real time over-the-air transmission. The use of Simulink and MATLAB for communication transceiver development will provide streaming access to the USRP2 without the steep learning curve associated with current workflows. These widely available software packages and the USRP2 will make digital communication system prototyping both affordable yet highly versatile, enabling researchers and industry engineers to conduct studies into new wireless communications and networking architectures including cognitive radio. Furthermore, the interface will allow users to become familiar with tools used in industry while learning communications and networking concepts.

"This thesis presents technologies that integrate field programmable gate arrays (FPGAs), model-driven design tools, and software-defined radios (SDRs). Specifically, an assessment of current state-of-the-art practices applying model-driven development techniques targeting SDR systems is conducted. FPGAs have become increasingly versatile computing devices due to their size and resource enhancements, advanced core generation, partial reconfigurability, and system-on-a-chip (SoC) implementations. Although FPGAs possess relatively better performance per watt when compared to central processing units (CPUs) or graphics processing units (GPUs), FPGAs have been avoided due to long development cycles and higher implementation costs due to significant learning curves and low levels of abstraction associated with the hardware description languages (HDLs). This thesis conducts a performance assessment of SDR designs using both a model-driven design approach developed with Mathworks HDL Coder and a hand-optimized design approach created from the model-driven VHDL. Each design was implemented on the FPGA fabric of a Zynq-7000 SoC, using a Zedboard evaluation platform for hardware verification. Furthermore, a set of guidelines and best practices for applying model-driven design techniques toward the development of SDR systems using HDL Coder is presented."

This thesis investigates the design and implementation of wireless communication system over the GNU Radio. Wireless applications are on the rise with advent of new devices, therefore there is a need to transfer the hardware complexity to software. This development enables software radio function with minimum hardware dependency. the purpose of this thesis is to design a system that will transmit compressed data via Software Defined Radio (SDR). Some parameters such as modulation scheme, bit rate can be changed to achieve the desired quality of service. in this thesis GNU (GNU’s not unix) radio is used while the hardware structure is Universal Software Radio Peripheral (USRP). in order to accomplish the goal, a compression technique called H264 (MPEG_4) encoding is applied for converting data into compressed format. the encoder was implemented in C++ to get compressed data. After encoding, the transmitter reads the compressed data and starts modulation. After modulation, the transmitter put the packets into USRP and sends it to the receiver. Once packets are received they are demodulated and then decoded to recover the original data.

Répondre aux contraintes des architectures reconfigurables pour des systèmes véhiculaires n'est pas toujours une tâche aisée. Des solutions existent dans le domaine de la radio logicielle où des plateformes flexibles qui prennent en charge un large éventail de différentes standards de communication sans fil peuvent être conçus. Une de ces architectures est la plateforme ExpressMIMO qui est développée par Eurecom et Télécom ParisTech. Les objectifs principales de cette thèse sont de proposer le premier prototype d'un récepteur pour ExpressMIMO, d'évaluer le potentiel de la plateforme pour les standards ayant des latences critiques, d'identifier des goulots d'étranglement et de proposer des solutions pour surmonter ces limitations. Comme standard, IEEE 802.11p a été choisi qui spécifie la communication entre des véhicules. Au-delà, nous étudions une possible exécution multimodal du 802.11p et du DAB sur ExpressMIMO. Notre analyse lors des expérimentations sur une cible FPGA révèle que le Front-End Processor DSP est lourdement chargé et que le temps de configuration requis dépasse le temps d'exécution. Pour relever ce défi nous proposons un Application Specific Instruction-Set Processor (ASIP) comme solution lorsque les contraintes de latence sont fortes. Pour compléter la chaîne de réception, nous présentons enfin un premier prototype de Préprocesseur qui connecte les convertisseurs A/D et D/A avec les autres composants de la bande de base. Dans ce contexte nous présentons un convertisseur générique et flexible pour le ré-échantillonnage qui travaille sur des rapports fractionnaires de fréquence d'échantillonnage. / Dealing with the requirements of reconfigurable radio architectures in the vehicular domain is a very challenging task. Solutions can be found in the context of Software Defined Radio (SDR). Under its umbrella, flexible hardware platforms that support a wide range of different wireless communication standards are designed. One of them is the OpenAirInterface ExpressMIMO platform that is developed by Eurecom and Télécom ParisTech. Main objectives of this thesis are to propose the first receiver chain prototype for ExpressMIMO, to assess the applicability of the platform for latency critical standards, to identify design bottlenecks and to propose and implement solutions to overcome the identified limitations. Standard of interest in this context is IEEE 802.11p which is required for the Car-to-Car communication. Our analysis reveals that the Front-End Processing (FEP) DSP engine is heavily charged and that the required configuration time outreaches the pure execution time for short vectors. To meet this challenge we introduce an Application Specific Instruction-Set Processor (ASIP) as the solution of choice when dealing with strong latency requirements. To complete the receiver chain we further present a first Preprocessor prototype which connects the external A/D and D/A converters with the remaining baseband engine. In this context we focus on a generic, flexible and hardware optimized Sample Rate Converter (SRC) that is operating on fractional ratios. As the combination of Car-to-Car and Car-to-Infrastructure communications within only device enables various new applications for future cars we finally investigate on a possible multimodal execution of 802.11p and DAB on the chosen target platform.

Main topic of this thesis is development of software for capture and analysis of RFID communication in UHF band (standard EPC Class-1 Generation-2). One part of the work is focused on the basics of the RFID systems, software defined radio concept and graphical programming language LabVIEW. Main part of this thesis is discussing the developed software itself, its methods and principles. Next part is dedicated to present the graphical user interface of created application and its functionality. Last part of this thesis contains examples of captured and analysed processes in UHF RFID communication.

The Software Communications Architecture (SCA) specification defines a framework that allows modular software components to be developed and assembled to build larger radio applications. The specification allows for these components to be distributed among a set of computing hardware and to be connected by standard interfaces. This research aims to build a spatially distributed SCA application for the Open Source SCA Implementation: Embedded (OSSIE) implementation using low-cost Universal Software Radio Peripheral (USRP) hardware. The system collects signals from multiple spatially distributed collection devices and use those signals to compute precision estimates for the location of emitters using time difference of arrival (TDOA) computations. Several OSSIE components and tools are developed to support this research. Results are presented showing the capabilities of the geolocation system. / Master of Science

No description available.

Digital communications devices designed with application-specific integrated circuit (ASIC) technology suffer from one very significant limitation�the integrated circuits are not programmable. Therefore, deploying a new algorithm or an updated standard requires new hardware. Field-programmable gate arrays (FPGAs) solve this problem by introducing what is essentially reconfigurable hardware. Thus, digital communications devices designed on FPGAs are capable of accommodating multiple communications protocols without the need to deploy new hardware, and can support new protocols in a matter of seconds. In addition, FPGAs provide a means to update systems that are physical difficult to access. For these reasons, FPGAs provide us with an ideal platform for implementing adaptive communications algorithms. This thesis focuses on using FPGAs to implement an adaptive digital communications system. Using the Universal Software Radio Peripheral (USRP) as a base, this thesis aims to create a highly-adaptive, plug and play software-defined radio (SDR) that fits CubeSat form-factor satellites. Such a radio platform would enable CubeSat engineers to develop new satellites faster and with lower costs. This thesis presents a new system, the COSMIAC CubeSat SDR, that adapts the USRP platform to better suit the space and power limitations of a CubeSat.

This thesis describes the work related to an interferer rejection system employing frequency analysis and cancellation through phase-opposed signal injection. The first device in the frequency analysis chain, an analog fast Fourier transform application-specific integrated circuit (ASIC), was improved upon. The second device, a chained fast Fourier transform followed by a frequency analysis module employing cross-correlation for signal detection was specified, designed and implemented in VHDL.

The design and development of a software defined radio (SDR) receiver prototype has been completed. The goal is to replace the existing automatic identification system (AIS) manufactured by Vesper Marine with a software driven system that reduces costs and provides a high degree of reconfigurability. One of the key concepts of the SDR is the consideration of directly digitizing the radio frequency (RF) signal using subsampling. This idea arises from the ambition to implement an analog-to-digital converter (ADC) as close to the antenna interface as practically possible. Thus, majority of the RF processing is encapsulated within in the digital domain. Evaluation of a frequency planning strategy that utilizes a combination of subsampling and oversampling will illustrate how the maritime bandwidth is aliased to a lower frequency. An analog front-end (AFE) board was constructed to implement the frequency planning strategy so that the digitized bandwidth can be streamed into a field programmable gate array (FPGA) for real-time processing. Research is shown on digital front-end (DFE) techniques that condition the digitized maritime signal for baseband processing. The process of a digital down converter (DDC) is conducted by an FPGA, which acquired the in-phase and quadrature signals. By implementing a digital signal processor (DSP) for baseband processing, demodulation on an AIS test signal is evaluated. The SDR prototype achieved a receiver sensitivity of -113dBm, outperforming the required sensitivity of -107dBm specified in the International Electrotechnical Commission (IEC) 62287-1 standard for AIS applications [1].