The motivation of this research is to study different cache designs for on-chip caches that improve processor performance and at the same time minimize the degradation to system performance caused by an increase in the processor memory traffic. As VLSI technology advances we can have bigger and more complex on-chip caches that could not have been possible a few years ago. Results derived from on-chip caches and performance issues are basically similar to off-chip caches. In this study, we will concentrate on single level on-chip caches though there are many interesting issues relating system performance, memory traffic and multi-level caches. / Graduation date: 1992

Copy of author's previously published article inserted. / Bibliography: leaves 240-246. / xvi, 246 leaves : ill. ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / This thesis examines cache coherence protocols designed for use in bus connected shared memory multiprocessors. / Thesis (Ph.D.)--University of Adelaide, Dept. of Computer Science, 1997?

by Leung Wing Man. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1996. / Includes bibliographical references (leaves 73-75). / Abstract --- p.i / Acknowledgements --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Background --- p.7 / Chapter 2.1 --- What is Mobile Computing? --- p.7 / Chapter 2.1.1 --- Applications of Mobile Computing --- p.8 / Chapter 2.1.2 --- New Challenges of Mobile Computing --- p.9 / Chapter 2.2 --- Related Work --- p.12 / Chapter 2.2.1 --- Lazy Replicated File Service --- p.12 / Chapter 2.2.2 --- Dividing the Database into Clusters --- p.14 / Chapter 2.2.3 --- Applying Causal Consistency --- p.15 / Chapter 2.3 --- Summary --- p.16 / Chapter 2.4 --- Serializability and Concurrency Control --- p.17 / Chapter 3 --- System Model and Suggested Protocol --- p.20 / Chapter 3.1 --- System Model --- p.20 / Chapter 3.2 --- Cache Management --- p.21 / Chapter 3.2.1 --- Version Control Mechanism --- p.22 / Chapter 3.2.2 --- Cache Consistency --- p.22 / Chapter 3.2.3 --- Request Data from Servers --- p.25 / Chapter 3.2.4 --- Invalidation Report --- p.27 / Chapter 3.2.5 --- Data Broadcasting --- p.30 / Chapter 4 --- Simulation Study --- p.32 / Chapter 4.1 --- Physical Queuing Model --- p.32 / Chapter 4.2 --- Logical System Model --- p.33 / Chapter 4.3 --- Parameter Setting --- p.34 / Chapter 4.4 --- The Significance of the Length of Invalidation Range --- p.37 / Chapter 4.4.1 --- Performance with Different Invalidation Range --- p.38 / Chapter 4.4.2 --- Increasing the Update Frequency --- p.40 / Chapter 4.4.3 --- Impact of Piggybacking Popular Data --- p.41 / Chapter 4.4.4 --- Increasing the Disconnection Period --- p.42 / Chapter 4.5 --- Comparison of the Proposed Protocol with the Amnesic Terminal Protocol --- p.44 / Chapter 4.5.1 --- Setting a Short Timeout Period --- p.45 / Chapter 4.5.2 --- Extending the Timeout Period --- p.46 / Chapter 4.5.3 --- Increasing the Frequency of Temporary Disconnection --- p.48 / Chapter 4.5.4 --- Increasing the Frequency of Crossing Boundaries --- p.49 / Chapter 4.6 --- Evaluate the Performance Gain with Piggybacking Message --- p.50 / Chapter 4.6.1 --- Adding Piggybacking Messages --- p.51 / Chapter 4.6.2 --- Reducing the Number of Popular Data --- p.52 / Chapter 4.6.3 --- Increasing the Frequency of Updates --- p.53 / Chapter 4.7 --- Behaviour of the Proposed Protocol --- p.54 / Chapter 4.7.1 --- Finding Maximum Number of Mobile Computers --- p.54 / Chapter 4.7.2 --- Interchanging the Frequency of Read-Only and Update Transactions --- p.55 / Chapter 5 --- Partially Replicated Database System --- p.57 / Chapter 5.1 --- Proposed Amendments --- p.57 / Chapter 5.1.1 --- Not Cache Partially Replicated Data ( Method 1 ) --- p.58 / Chapter 5.1.2 --- Drop Partially Replicated Data ( Method 2 ) --- p.59 / Chapter 5.1.3 --- Attaching Server-List ( Method 3 ) --- p.59 / Chapter 5.2 --- Experiments and Interpretation --- p.60 / Chapter 5.2.1 --- Partially Replicated Data with High Accessing Probability --- p.61 / Chapter 5.2.2 --- Reducing the Cache Size --- p.64 / Chapter 5.2.3 --- Partially Replicated Data with Low Accessing Probability --- p.65 / Chapter 6 --- Conclusions and Future Work --- p.70 / Chapter 6.1 --- Future Work --- p.72 / Bibliography --- p.73 / Chapter A --- Version Control Mechanism for Servers --- p.76

Thesis (Ph. D.)--Hong Kong University of Science and Technology, 2002. / Includes bibliographical references (leaves 146-158). Also available in electronic version. Access restricted to campus users.

Thesis (Ph. D.)--University of Washington, 2002. / Vita. Includes bibliographical references (p. 103-109).

Thesis (Ph. D.)--University of Washington, 1997. / Vita. Includes bibliographical references (leaves [76]-77).

Thesis (M.S.)--Drexel University, 2003. / Includes abstract. Includes bibliographical references (leaves 64-65).

Not available / text

No description available.

Thesis (Ph. D.)--University of Texas at Austin, 2003. / Supervisor: Mike Dahlin and Lorenzo Alvisi. Vita. Includes bibliographical references. Available also from UMI Company.