by Yu, Lawrence Kwok Cheung. / Thesis (M.B.A.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references (leaves 46-47). / ABSTRACT --- p.iii / TABLE OF CONTENTS --- p.iv / LIST OF TABLES --- p.vi / ACKNOWLEDGMENT --- p.vii / Chapter / Chapter I. --- INTRODUCTION --- p.1 / Benefits of Outsourcing --- p.1 / Strategic Benefits --- p.1 / Financial Benefits --- p.2 / Operational Benefits --- p.3 / Human Resources Benefits --- p.3 / Risks of Outsourcing --- p.4 / Strategic Risks --- p.4 / Financial Risks --- p.4 / Operational Risks --- p.5 / Human Resources Risks --- p.6 / Outsourcing Issues --- p.7 / Feasibility and Planning --- p.7 / Outsourcing Candidate Identification --- p.8 / Outsourcing Engagement --- p.10 / Managing the Outsourcing Contract --- p.12 / Human Resources Development --- p.14 / Outsourcing Post-mortem Analysis --- p.14 / Other Important Findings --- p.15 / Outsourcing Trends --- p.16 / Chapter II. --- MOTOROLA SPS CONSUMER SYSTEMS GROUP --- p.19 / Background --- p.19 / CSG Needs --- p.20 / Analyzing Outsourcing to Cadence --- p.21 / Chapter III. --- REVIEW OF CADENCE DESIGN SYSTEMS --- p.22 / Company Background --- p.22 / Cadence Design Services --- p.23 / Multimedia Design Services --- p.26 / Recent Cadence Design Services News --- p.27 / Chapter IV. --- MOTOROLA SPS AND CADENCE --- p.28 / Past Cadence Outsourcing Projects --- p.28 / Views of Colleagues on Past Cadence Outsourcing Projects --- p.30 / Views of Colleagues on Outsourcing Design Work to Cadence --- p.32 / Chapter V. --- ANALYSIS --- p.35 / Technical Issues --- p.35 / Economic Issues --- p.36 / Legal Issues --- p.37 / Operational Issues --- p.37 / Sensitivity Issues --- p.38 / Other Analyses --- p.39 / Chapter VI. --- RECOMMENDATIONS AND CONCLUSIONS --- p.41 / Other Recommendations --- p.42 / Conclusions --- p.43 / APPENDIX --- p.44 / BIBLIOGRAPHY --- p.46

This thesis presents the design of a mixed-signal CMOS multiplier implemented with short-channel PMOS transistors. The multiplier presented here forms the product of a differential input voltage and a five-bit digital code. A TSMC 0.18 µm MOSFET model is used to simulate the circuit in Cadence Design Systems. The research presented in this thesis reveals a configuration that allows the multiplier to run at a speed of 8.2 GHz with end-point nonlinearity less than 5%. The high speed and low nonlinearity make this circuit ideal for applications such as filtering and digital to analog conversion.