This thesis presents the design and implementation of PMOS-based integrated charge pumps with extended voltage range and their regulation circuits in a standard process. The performance of charge pumps are evaluated by their output resistances and power conversion efficiencies. Formulas which describe the charge pump characteristics are developed and presented. Existing charge pumps are analyzed and studied to understand their limitations in generating high voltages and achieving high performance. The proposed charge pump structures are designed to use PMOS switches to alleviate the high voltage stresses across transistors by biasing their bulk independently. The voltages across transistors and capacitors are kept within the suggested voltage rating (VDD)regardless of how high the output voltage is, thus the maximum voltage range is extended and no longer limited by the breakdown voltages of the devices. The charge pump circuits only need low-voltage devices and standard processes, and can be easily integrated in a digital or mixed-signal design. The proposed charge pump regulation circuits include a voltage divider, a voltage controlled ring oscillator and a feedback operational amplifier. The regulation circuits are able to adjust the clock frequency to regulate the charge pump to a steady output voltage (set by the reference voltage) under a large range of current loads. A test chip including the proposed charge pumps and regulation circuits was fabricated in a 0.18 um digital CMOS process provided by Taiwan Semiconductor Manufacturing Company (TSMC). The proposed charge pumps were tested and demonstrated the reliable generation of output voltages up to 11.47 V using only low-voltage devices. The simulation and measurement results have been presented and compared, demonstrating the functionality and performance of the proposed circuits. / Kapik Integration, Mitacs

L’industrie microélectronique arrive à concevoir des transistors atteignant dimensions de l’ordre de la dizaine de nanomètres. Et ce faisant elle tend atteindre ses limites en terme de réduction des dimensions des transistors CMOS. Or à ces dimensions, la fiabilité et la variabilité des dispositifs prennent une ampleur critique en ce qui concerne les prédictions de durée de vie et de garantie des composants. Parmi les aspects critiques, la dégradation NBTI (Négative Bias Temperature Instability) représente l’un des plus gros défis en termes de fiabilité. Cette dégradation tire son origine d’un piégeage de charge dans l’oxyde de grille et est responsable pour une grande partie de la dégradation des transistors. A l’aide d’un important travail expérimental, nous avons caractérisé à l’aide de mesure rapide les cinétiques de dégradation et de relaxation de la dégradation NBTI, puis nous avons travaillé sur la modélisation des phases de stress et de relaxation. Nous sommes parvenues à créer un modèle pour le stress et la relaxation que nous avons éprouvé sur un certain nombre de nœuds technologiques allant du 14nm FDSOI au 180nm Bulk. Nous avons aussi évalué l’impact de certains changements de procédées de fabrication sur la dégradation NBTI.Enfin nous proposons une étude poussée de la variabilité induite par le NBTI et du modèle DCM (Defect centric Model) permettant de modéliser cette variabilité. Nous proposons alors une correction mathématique de ce modèle, et la possibilité de le réécrire afin de pouvoir l’utiliser pour un plus grand nombre de défauts. Enfin nous mettrons ce modèle en échec sur les prédictions qu’il fait de défauts et nous proposons un nouveau modèle sous la forme d’un DCM à deux défauts ou DDCM (Dual Defect Centric Model).Mots-clés : Microélectronique, FDSOI, Bulk, variabilité, NBTI, caractérisation électrique, modélisation. / The microelectronics industry is able to design transistors reaching dimensions of the order of ten nanometers. And doing this, we reaching the limits in terms of size reduction of CMOS transistors. At these dimensions, the reliability and variability of the devices is critical in terms of lifetime prediction and component warranty. Among the critical aspects, NBTI (Negative Bias Temperature Instability) degradation represents one of the biggest challenges in terms of reliability. This degradation coming from a charge trapping in the gate oxide is responsible for a large part of the degradation of the transistors. Performing a huge experimental work based on the characterization of the kinetic of degradation and relaxation of the NBTI degradation with rapid measurements, allowing us to work on the modeling of the stress and relaxation phases of NBTI degradation. We have successfully create a model for stress and relaxation of the NBTI degradation. These models were then tested on several technological nodes from 14nm FDSOI to 180nm Bulk. We also study the impact of some process changes on NBTI degradation. Finally, we propose a detailed study of the variability induced by the NBTI and the DCM model (Defect centric Model) allowing to model this variability. We also propose a mathematical correction of this model but also another mathematical expression of this model allowing to use it for a large number of defects. Enfin, nous prouvons que DCM est défectueux dans sa prédiction du nombre de défauts et nous proposons un nouveau modèle sous la forme d'un DCM avec deux défauts ou DDCM (Dual Defect Centric Model).

No / Introduction Patients represent an important and as yet untapped source of information about the factors that contribute to the safety of their care. The aim of the current study is to test the reliability and validity of the Patient Measure of Safety (PMOS), a brief patient-completed questionnaire that allows hospitals to proactively identify areas of safety concern and vulnerability, and to intervene before incidents occur. Methods 297 patients from 11 hospital wards completed the PMOS questionnaire during their stay; 25 completed a second 1 week later. The Agency for Healthcare Research and Quality (AHRQ) safety culture survey was completed by 190 staff on 10 of these wards. Factor structure, internal reliability, test-retest reliability, discriminant validity and convergent validity were assessed. Results Factor analyses revealed 8 key domains of safety (eg, communication and team work, access to resources, staff roles and responsibilities) explaining 58% variance of the original questionnaire. Cronbach’s α (range 0.66–0.89) and test-retest reliability (r=0.75) were good. The PMOS positive index significantly correlated with staff reported ‘perceptions of patient safety’ (r=0.79) and ‘patient safety grade’ (r=−0.81) outcomes from the AHRQ (demonstrating convergent validity). A multivariate analysis of variance (MAMOVA) revealed that three PMOS factors and one retained single item discriminated significantly across the 11 wards. Discussion The PMOS is the first patient questionnaire used to assess factors contributing to safety in hospital settings from a patient perspective. It has demonstrated acceptable reliability and validity. Such information is useful to help hospitals/units proactively improve the safety of their care.

Submitted by Thiago Henriques Fernandes (thiagohenriques@gmail.com) on 2016-05-20T17:00:09Z No. of bitstreams: 1 Dissertação Versão Final Thiago Henriques Fernandes MPA FGV_Protocolo.pdf: 1615948 bytes, checksum: 6be3daa2d29a71d66c8fb7a4efd86c53 (MD5) / Approved for entry into archive by Ana Luiza Holme (ana.holme@fgv.br) on 2016-05-20T17:25:32Z (GMT) No. of bitstreams: 1 Dissertação Versão Final Thiago Henriques Fernandes MPA FGV_Protocolo.pdf: 1615948 bytes, checksum: 6be3daa2d29a71d66c8fb7a4efd86c53 (MD5) / Made available in DSpace on 2016-05-20T17:43:45Z (GMT). No. of bitstreams: 1 Dissertação Versão Final Thiago Henriques Fernandes MPA FGV_Protocolo.pdf: 1615948 bytes, checksum: 6be3daa2d29a71d66c8fb7a4efd86c53 (MD5) Previous issue date: 2016-05-06 / The objective of this work was to identify what are the main divergences found between what the theory preconizes as scope and approach of the Project Management Offices (PMOs) and what really happens when practice is observed on site. Such intend was achieved with the support of a case study analysis. The theme may be considered relevant based on the fact that it provides a better comprehension about how the PMOs structures really operate. Specially regarding to scope, that is, whether the PMO is a Program-Project, a Departmental PMO, or a Corporate PMO, and regarding its range, that is, if its action is operational, tactical or strategic. Qualitative methodology was used in this research, through a case study approach. A large size manufacturing company not structured by projects was chosen to be evaluated. This company has a complex organizational structure and such characteristic makes possible a comprehensive study. The performance of the PMOs addressed in the case study was discussed taking in consideration the literature and also the information collected from the participant observation. The results of this work allows to conclude that the assumption of the research, that there are divergences between what the theory preconizes as scope and approach of the PMOs and what really happens on practice, is confirmed through the case study. Beyond that, there is not a clear causality relation between the amplitude of action of those PMOs and its hierarchic position within the organization. Also there is not a pattern of action of the PMOs when compared to functions that they perform. Finally, recommendations were made related to the case study presented. The main ones are shown as follows. It is important to hold a multi case study for a better comprehension of the theme with at least one company structured by projects and other one non-structured by projects in order to compare the performance of their PMOs aiming to better understand the theme. To include more stakeholders among the group of the interviewed people within the case study. To hold a survey with various companies of various segments inside the national territory. Also to perform a study where it may be verified whether different organizational typologies may affect the practice of PMOs in the organizations. / Neste trabalho, o objetivo é identificar, a partir da análise de um estudo de caso, quais são as principais divergências encontradas quando se compara o que a teoria preconiza como o escopo e a abordagem dos Project Management Offices - PMOs e o que acontece na prática, no que diz respeito à real atuação destas estruturas. O tema pode ser considerado relevante devido ao fato de fornecer uma melhor compreensão sobre como as estruturas de PMO realmente atuam, principalmente no que diz respeito ao escopo, isto é, se o PMO é um Programa-Projeto, um PMO Departamental ou um PMO Corporativo e relativamente a sua amplitude, ou seja, se sua atuação é operacional, tática ou estratégica. Para este estudo foi utilizada a metodologia qualitativa, por meio da abordagem de estudo de caso. Foi selecionada uma empresa de grande porte do setor de manufatura não estruturada por projeto para avaliação. A empresa do estudo de caso possui uma estrutura organizacional complexa que possibilita um estudo abrangente. A atuação dos PMOs do estudo de caso foi discutida à luz da revisão de literatura e levando-se em conta, também, as informações colhidas a partir da observação participante. Os resultados deste trabalho permitem concluir que o pressuposto defendido, que é a existência de divergências entre o que a teoria preconiza como escopo e abordagem do PMO e a real atuação dos PMOs, foi confirmado através do estudo de caso; além disso, não existe relação de causalidade clara entre o escopo de atuação dos PMOs e sua posição hierárquica dentro da empresa; e não existe uma atuação padrão destas estruturas, quando comparadas às funções que elas exercem. Por fim, são apresentadas recomendações relativas ao estudo de caso realizado, ou seja, é importante realizar um estudo multicasos entre ao menos uma empresa não estruturada por projeto e outra estruturada por projeto e comparar a atuação dos seus PMOs para melhor compreensão do tema, incluir mais stakeholders no grupo de entrevistados dentro do estudo de caso, realizar um survey com várias empresas de vários segmentos dentro do território nacional e um possível estudo onde seja verificado se tipologias diferentes de estruturas organizacionais podem afetar a atuação práticas dos PMOs.

This Master`s thesis deals with properties of current feedback operational amplifier. The main goal of this work is creation design process of current feedback operational amplifier by using CMOS technology AMIS 0,7 µm. Next goal of this work is attestation of funciton our design process. Last goal is creation the datasheet of our amplifier.

Yes / The Primary Care Patient Measure of Safety (PC PMOS) is designed to capture patient feedback about the contributing factors to patient safety incidents in primary care. It required further reliability and validity testing to produce a robust tool intended to improve safety in practice. Method 490 adult patients in nine primary care practices in Greater Manchester, UK, completed the PC PMOS. Practice staff (n = 81) completed a survey on patient safety culture to assess convergent validity. Confirmatory factor analysis (CFA) assessed the construct validity and internal reliability of the PC PMOS domains and items. A multivariate analysis of variance was conducted to assess discriminant validity, and Spearman correlation was conducted to establish test–retest reliability. Results Initial CFA results showed data did not fit the model well (a chi-square to df ratio (CMIN/DF) = 5.68; goodness-of-fit index (GFI) = 0.61, CFI = 0.57, SRMR = 0.13  and root mean square error of approximation (RMSEA) = 0.10). On the basis of large modification indices (>10), standardised residuals >± 2.58 and assessment of item content; 22 items were removed. This revised nine-factor model (28 items) was found to fit the data satisfactorily (CMIN/DF = 2.51; GFI = 0.87, CFI = 0.91, SRMR = 0.04  and RMSEA = 0.05). New factors demonstrated good internal reliability with average inter-item correlations ranging from 0.20 to 0.70. The PC PMOS demonstrated good discriminant validity between primary care practices (F = 2.64, df = 72, p < 0.001) and showed some association with practice staff safety score (convergent validity) but failed to reach statistical significance (r = −0.64, k = 9, p = 0.06). Conclusion This study led to a reliable and valid 28-item PC PMOS. It could enhance or complement current data collection methods used in primary care to identify and prevent error. / NIHR Greater Manchester Patient Safety Translational Research Centre.

A new shallow junction formation process, based on selective silicon etching followed by selective growth of in situ B-doped SiGe, is presented. The approach is advantageous compared to conventional ion implantation followed by thermal activation, because perfectly abrupt, low resistivity junctions of arbitrary depth can be obtained. In B-doped SiGe layers, the active doping concentration can exceed the solid solubility in silicon because of strain compensation. In addition, the compressive strain induced in the Si channel can improve drivability through increased hole mobility. The process is integrated by performing the selective etching and the selective SiGe growth in the same reactor. The main advantage of this is that the delicate gate oxide is preserved. The silicon etching process (based on HCl) is shown to be highly selective over SiO2 and anisotropic, exhibiting the densely packed (100), (311) and (111) surfaces. It was found that the process temperature should be confined between 800 ºC, where etch pits occur, and 1000 ºC, where the masking oxide is attacked. B-doped SiGe layers with a resistivity of 5×10-4 Ωcm were obtained. Well-behaved pMOS transistors are presented, yet with low layer quality. Therefore integration issues related to the epitaxial growth, such as selectivity, loading effect, pile-up and defect generation, were investigated. Surface damage originating from reactive-ion etching of the sidewall spacer and nitride residues from LOCOS formation were found to degrade the quality of the SiGe layer. Various remedies are discussed. Nevertheless, high-quality selective epitaxial growth could not be achieved with a doping concentration in the 1021 cm-3 range. The maximum doping level resulting in a high-quality layer, with the loading effect taken into account, was 6×1020 cm-3. After this careful process optimization, a high-quality layer was obtained in the recessed areas. Finally, Ni mono-germanosilicide was investigated as a material for contact formation to the epitaxial SiGe layers in the recessed source and drain areas. The formation temperature is 550 ºC and it is stable up to 700 ºC. The observation of a recessed step and lateral growth of the silicide led to a detailed treatment of the contact resistivity of the NiSi0.8Ge0.2/Si0.8Ge0.2 interface using 2-D as well as 3-D modeling. Different values were obtained for square shaped and rounded contacts, 5.0x10-8 Ωcm2 and 1.4x10-7 Ωcm2, respectively. / QC 20101028

<p>A new shallow junction formation process, based on selective silicon etching followed by selective growth of in situ B-doped SiGe, is presented. The approach is advantageous compared to conventional ion implantation followed by thermal activation, because perfectly abrupt, low resistivity junctions of arbitrary depth can be obtained. In B-doped SiGe layers, the active doping concentration can exceed the solid solubility in silicon because of strain compensation. In addition, the compressive strain induced in the Si channel can improve drivability through increased hole mobility. The process is integrated by performing the selective etching and the selective SiGe growth in the same reactor. The main advantage of this is that the delicate gate oxide is preserved. The silicon etching process (based on HCl) is shown to be highly selective over SiO₂ and anisotropic, exhibiting the densely packed (100), (311) and (111) surfaces. It was found that the process temperature should be confined between 800 ºC, where etch pits occur, and 1000 ºC, where the masking oxide is attacked. B-doped SiGe layers with a resistivity of 5×10-⁴ Ωcm were obtained. Well-behaved pMOS transistors are presented, yet with low layer quality. Therefore integration issues related to the epitaxial growth, such as selectivity, loading effect, pile-up and defect generation, were investigated. Surface damage originating from reactive-ion etching of the sidewall spacer and nitride residues from LOCOS formation were found to degrade the quality of the SiGe layer. Various remedies are discussed. Nevertheless, high-quality selective epitaxial growth could not be achieved with a doping concentration in the 1021 cm-3 range. The maximum doping level resulting in a high-quality layer, with the loading effect taken into account, was 6×10²⁰cm-³. After this careful process optimization, a high-quality layer was obtained in the recessed areas. Finally, Ni mono-germanosilicide was investigated as a material for contact formation to the epitaxial SiGe layers in the recessed source and drain areas. The formation temperature is 550 ºC and it is stable up to 700 ºC. The observation of a recessed step and lateral growth of the silicide led to a detailed treatment of the contact resistivity of the NiSi₀.₈Ge_0.2/Si_0.8Ge_0.2 interface using 2-D as well as 3-D modeling. Different values were obtained for square shaped and rounded contacts, 5.0x10^-8 Ωcm² and 1.4x10^-7 Ωcm², respectively.</p>

Depuis plus de trente ans, la micro-électronique subit une évolution continue permettant de répondre à une demande croissante en terme de rapidité et de complexité des circuits intégrés. Cette évolution a été rendue possible grâce à la miniaturisation des composants, qui atteint aujourd'hui les limites physiques des matériaux utilisés en technologie CMOS. Parmi les nombreux problèmes et limitations liés à la réduction de la longueur de canal et de l'épaisseur de l'oxyde (effets de canal court, effets quantiques, déplétion de grille, claquage, quasi-claquage, SILC ¿), nous nous sommes centrés sur la structure PMOS (grille dopée bore), et en particulier sur la réduction de la pénétration du bore depuis la grille vers le substrat, responsable des instabilités de la tension de seuil, et sur l'amélioration de la fiabilité de l'isolant de grille ultra-mince, qui définit sa durée de vie. Un premier chapitre est consacré à une étude bibliographique portant sur les solutions technologiques actuelles répondant à ce problème, et il apparaît intéressant d'utiliser d'une part une grille déposée amorphe, et d'autre part d'introduire de l'azote à l'interface grille/oxyde. A partir de là, nous proposons une alternative technologique qui consiste à développer une grille de 200 nm d'épaisseur à base de silicium dopé azote (NIDOS) déposé amorphe à partir de disilane Si2H6 et d'ammoniac NH3. Un second chapitre concerne l'élaboration des films de NIDOS de 200nm, ainsi qu'à leur caractérisation électrique et mécanique. Nous montrons que la grille doit être composée d'une structure bi-couche comprenant 5nm de NIDOS et 195 nm de silicium afin de minimiser la résistivité totale de la grille. Dans un troisième chapitre, nous sommes intéressés au dopage bore par implantation ionique, et nous avons mis en évidence une forte réduction de la diffusion du bore dans les films de NIDOS. A partir de là, le NIDOS se présente comme une s olution intéressante afin de préserver l'intégrité de l'oxyde, et par là même la pénétration du bore dans le substrat. La fiabilité d'une structure capacitive polySi (P+)/NIDOS(5nm)/SiO2(4.5nm)/Si est étudiée dans un quatrième chapitre. Nous montrons électriquement d'une part le rôle de barrière à la diffusion du bore joué par le NIDOS et des résultats prometteurs en terme de tenue au claquage (Qbd=60C/cm_ à 0.1 A/cm_), et d'autre part des effets de déplétion de grille importants (>20%). Ce dernier point pourrait être amélioré en envisageant un recuit supplémentaire par RTP, ou bien en développant une grille dopée bore in-situ.

This thesis presents the modeling and fabrication of a new solid-state device meant to be used for digital logic circuits. Most current logic circuits are based on MOSFETs. The new logic device uses some of the same operating principles, but also relies on optical illumination to provide input power. In order to obtain the desired current-voltage behavior of the new device, the Silvaco (Atlas) device simulation was used to give some insight into the correct doping levels in the semiconductor and device geometries. Prototypes were fabricated on p-type silicon wafers using CMOS fabrication processes including oxide growth, photolithography, precise plasma or chemical wet etching, diffusion processes, and thin film evaporation. Electrical measurements were done by using an HP4156 parameter analyzer to measure several output voltage signals at one time while an illuminating the device with laser light. The current-voltage characteristics under different biasing conditions with an optical illumination condition were measured and showed characteristics similar to an nMOS transistor.