Orientador: Jose Alexandre Diniz / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-21T20:16:28Z (GMT). No. of bitstreams: 1 Biasotto_Cleber_D.pdf: 3795677 bytes, checksum: e4e2355f73ec8fb2ad7677cdf17f5daf (MD5) Previous issue date: 2012 / Resumo: Atualmente para atender à necessidade de fabricação dos sensores, dispositivos eletrônicos e circuitos integrados com dimensões micro e nanométricas, novos processo de custos e de thermal budgets reduzidos são necessários. Este trabalho apresenta o desenvolvimento de alguns destes novos processos alternativos para aplicação nesta fabricação. O trabalho está dividido em quatro partes: a primeira parte apresenta a obtenção e a caracterização de filmes isolantes de nitreto de silício para aplicação em microsensores, tais como o sensor de pressão. Estes filmes foram obtidos sobre substratos de Si em baixa temperatura (20°C) utilizando-se um reator de plasma do tipo ECRCVD (Electron Cyclotron Resonance - Chemical Vapor Deposition). Normalmente reatores do tipo Low Pressure Chemical Vapor Deposition (LPCVD) ou Plasma Enhanced - CVD (PECVD) em temperaturas maiores que 600ºC e 250ºC, respectivamente, são utilizados para essa aplicação. A caracterização dos plasmas ECR, que foram usados para as deposições dos nitretos, e a fabricação de membranas suspensas com estes filmes são apresentadas. A segunda parte apresenta a fabricação e a caracterização de diodos p+-n fabricados em camada de SiGe crescida por LPCVD sobre substrato de Si. Processo este alternativo em substituição aos executados em reatores epitaxiais de alto custo. Na terceira parte deste trabalho, é apresentado o desenvolvimento de processos em baixa temperatura para aplicação em diodos e tecnologia MOS (Metal-Oxide-Semiconductor). São apresentadas a fabricação e a caracterização elétrica dos capacitores MOS, utilizando as tecnologias ALD (Atomic Layer Deposition) e ICP (Inductively Coupled Plasma) para a obtenção em baixa temperatura dos dielétricos high-k de Al2O3 e SiON de porta MOS, respectivamente. Na quarta parte, são apresentadas também, a fabricação e a caracterização elétrica de diodos n+p utilizando a tecnologia de recozimento a laser. O desenvolvimento de capacitores MOS e diodos possibilitou a fabricação (usando processos em baixa temperatura (?400oC)) de n- e p-MISFETs (Metal- Insulator-Semiconductor Field Effect Transistors), como também a fabricação de um protótipo de transistor MOS de alta velocidade baseado em silício germânio chamado D-DotFET (Disposable Dot Field Effect Transistor). Os processos alternativos desenvolvidos nesta tese apresentam um enorme potencial para aplicação nas próximas gerações de dispositivos CMOS (Complementary Metal Oxide Semiconductor) de dimensões sub-22 nm / Abstract: Nowadays, to attend the needs of the fabrication of sensors, electronic devices and integrated circuits with dimensions of micro and nanometrics, new processes of reduced costs and thermal budgets are needed. This work presents the development of some of these alternative processes for this fabrication. This work is divided in four parts: the first part presents the synthesis and characterization of insulating films of silicon nitride for application in microsensors, such as pressure sensors. These films were deposited on Si substrates at low temperature (20°C) using an ECR-CVD (Electron Cyclotron Resonance - Chemical Vapor Deposition) plasma reactor. Normally, Low Pressure Chemical Vapor Deposition (LPCVD) or Plasma Enhanced CVD - (PECVD) reactors are used for this application with high temperature process higher than 600oC and 250oC, respectively. The characterization of ECR plasmas, which were used to get the silicon nitrides, and the fabrication of suspended membranes based on these nitrides are presented. The second part presents the fabrication and the characterization of p+-n silicon germanium (SiGe) diodes fabricated on SiGe layers, which were grown by LPCVD on Si substrate. The grown of SiGe layers by LPCVD is an alternative process to replace the high cost of epitaxial reactors. In the third part of this work is presented the development of low-temperature processes for application in diodes and MOS (Metal-Oxide-Semiconductor) technology. The fabrication at low temperature and electrical characterization of MOS capacitors, using technologies as: ALD (Atomic Layer Deposition) and ICP (Inductively Coupled Plasma) to get the Al2O3 and SiON high-k gate dielectrics of MOS capacitors are presented, respectively. In the four part, the fabrication and electrical characterization of n+-p diodes using the process of laser annealing are presented as well. The development of MOS capacitors and diodes have become feasible the fabrication (using processes at low temperature (? 400oC)) of n- and p-MISFETs (Metal- Insulator -Semiconductor Field Effect Transistors) and also the fabrication of a high speed MOS transistor prototype based on silicon germanium named D-DotFET (Disposable Dot Field Effect Transistor). In conclusion, the alternative processes developed in this thesis have shown to be a huge potential for application in next generations of CMOS (Complementary Metal Oxide Semiconductor) devices with sub- 22 nm dimensions / Doutorado / Eletrônica, Microeletrônica e Optoeletrônica / Doutor em Engenharia Elétrica

Depuis les années 1970, la taille des composants n’a cessé de diminuer. La réalisation de jonctions ultra-minces et fortement dopées est devenue un point clef dans la réduction des dispositifs microélectroniques. Les techniques de production doivent évoluer afin de répondre aux spécifications drastiques, en termes de taille des zones dopées et de leurs propriétés électriques, des prochains noeuds technologiques. Dans ce travail de thèse nous avons étudié le procédé d’activation au laser de dopants implantés par immersion plasma. Le laser à excimère utilisé (ArF) est absorbé dans moins de 10 nmde silicium, ce qui va permettre un recuit local. De plus, la courte durée d’impulsion va assurer un faible budget thermique, limitant la diffusion des dopants. En associant cette technique à l’implantation ionique par immersion plasma, dont l’intérêt est de pouvoir travailler à de très basses tensions d’accélération (quelques dizaines d’eV), nous pouvons réaliser des jonctions avec un fort taux d’activation sans diffusion. Après avoir présenté les différentes techniques de dopage pouvant être utilisées, nous avons décrit les dispositifs expérimentaux de traitement et de caractérisation utilisés. Des simulations ont permis de comprendre le rôle des paramètres laser sur le profil de température du siliciumen surface. Après avoir choisi le laser le plus adapté parmi les lasers ArF, KrF et XeCl (respectivement: 193 nm - 15 ns, 248 nm - 35 ns, 308 nm - 50 ns), nous avons observé l’effet du nombre de tirs et de la mise en forme de faisceau afin d’optimiser le procédé. Pour terminer, des inhomogénéités dues aux bords de faisceau ont été mises en évidence et étudiées afin d’enlimiter l’effet. / Since the 1970’s, the components size has steadily declined. The realization of highly-dopedultra shallow junctions became a key point in the reduction of microelectronic devices. Them anufacturing processes must evolve to meet the stringent specifications of the next technologynodes, in particular in terms of dimension and electrical properties of the doped area.In this thesis we have studied the process of laser annealing of dopants implanted by plasmaimmersion. The ArF excimer laser we used is absorbed in less than 10 nm of silicon, whichallows a local heating. Moreover, the short pulse duration provides a low thermal budget whichreduces the dopant diffusion. By combining this technique with plasma immersion ion implantation, which is interesting because of the very low acceleration voltage (few tens of eV), we can produce highly activated junctions without diffusion. After a presentation of the different doping techniques that may be used, we describe the experimental treatment and the characterization tools that we used. We have used numerical simulations to understand the role of the laser parameters on the temperature profile of the silicon surface. After choosing the most suitable laser between ArF, KrF and XeCl (respectively :193 nm - 15 ns, 248 nm - 35 ns, 308 nm - 50 ns), we studied the influence of the number of shots and beam shaping to optimize the process. Finally, inhomogeneities caused by the beam edgeshave been studied and identified in order to improve the laser scan process.

A new shallow junction formation process, based on selective silicon etching followed by selective growth of in situ B-doped SiGe, is presented. The approach is advantageous compared to conventional ion implantation followed by thermal activation, because perfectly abrupt, low resistivity junctions of arbitrary depth can be obtained. In B-doped SiGe layers, the active doping concentration can exceed the solid solubility in silicon because of strain compensation. In addition, the compressive strain induced in the Si channel can improve drivability through increased hole mobility. The process is integrated by performing the selective etching and the selective SiGe growth in the same reactor. The main advantage of this is that the delicate gate oxide is preserved. The silicon etching process (based on HCl) is shown to be highly selective over SiO2 and anisotropic, exhibiting the densely packed (100), (311) and (111) surfaces. It was found that the process temperature should be confined between 800 ºC, where etch pits occur, and 1000 ºC, where the masking oxide is attacked. B-doped SiGe layers with a resistivity of 5×10-4 Ωcm were obtained. Well-behaved pMOS transistors are presented, yet with low layer quality. Therefore integration issues related to the epitaxial growth, such as selectivity, loading effect, pile-up and defect generation, were investigated. Surface damage originating from reactive-ion etching of the sidewall spacer and nitride residues from LOCOS formation were found to degrade the quality of the SiGe layer. Various remedies are discussed. Nevertheless, high-quality selective epitaxial growth could not be achieved with a doping concentration in the 1021 cm-3 range. The maximum doping level resulting in a high-quality layer, with the loading effect taken into account, was 6×1020 cm-3. After this careful process optimization, a high-quality layer was obtained in the recessed areas. Finally, Ni mono-germanosilicide was investigated as a material for contact formation to the epitaxial SiGe layers in the recessed source and drain areas. The formation temperature is 550 ºC and it is stable up to 700 ºC. The observation of a recessed step and lateral growth of the silicide led to a detailed treatment of the contact resistivity of the NiSi0.8Ge0.2/Si0.8Ge0.2 interface using 2-D as well as 3-D modeling. Different values were obtained for square shaped and rounded contacts, 5.0x10-8 Ωcm2 and 1.4x10-7 Ωcm2, respectively. / QC 20101028

<p>A new shallow junction formation process, based on selective silicon etching followed by selective growth of in situ B-doped SiGe, is presented. The approach is advantageous compared to conventional ion implantation followed by thermal activation, because perfectly abrupt, low resistivity junctions of arbitrary depth can be obtained. In B-doped SiGe layers, the active doping concentration can exceed the solid solubility in silicon because of strain compensation. In addition, the compressive strain induced in the Si channel can improve drivability through increased hole mobility. The process is integrated by performing the selective etching and the selective SiGe growth in the same reactor. The main advantage of this is that the delicate gate oxide is preserved. The silicon etching process (based on HCl) is shown to be highly selective over SiO₂ and anisotropic, exhibiting the densely packed (100), (311) and (111) surfaces. It was found that the process temperature should be confined between 800 ºC, where etch pits occur, and 1000 ºC, where the masking oxide is attacked. B-doped SiGe layers with a resistivity of 5×10-⁴ Ωcm were obtained. Well-behaved pMOS transistors are presented, yet with low layer quality. Therefore integration issues related to the epitaxial growth, such as selectivity, loading effect, pile-up and defect generation, were investigated. Surface damage originating from reactive-ion etching of the sidewall spacer and nitride residues from LOCOS formation were found to degrade the quality of the SiGe layer. Various remedies are discussed. Nevertheless, high-quality selective epitaxial growth could not be achieved with a doping concentration in the 1021 cm-3 range. The maximum doping level resulting in a high-quality layer, with the loading effect taken into account, was 6×10²⁰cm-³. After this careful process optimization, a high-quality layer was obtained in the recessed areas. Finally, Ni mono-germanosilicide was investigated as a material for contact formation to the epitaxial SiGe layers in the recessed source and drain areas. The formation temperature is 550 ºC and it is stable up to 700 ºC. The observation of a recessed step and lateral growth of the silicide led to a detailed treatment of the contact resistivity of the NiSi₀.₈Ge_0.2/Si_0.8Ge_0.2 interface using 2-D as well as 3-D modeling. Different values were obtained for square shaped and rounded contacts, 5.0x10^-8 Ωcm² and 1.4x10^-7 Ωcm², respectively.</p>