published_or_final_version / abstract / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

by Leung Tin Chi. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 106-108). / Abstracts in English and Chinese. / Abstract / Acknowledgements / Table of Contents / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Balun Structures --- p.2 / Chapter 1.2 --- Balun Parameters --- p.4 / Chapter 1.3 --- LTCC Multi-layer Balun --- p.5 / Chapter 1.4 --- Original Contributions of The Thesis --- p.7 / Chapter Chapter 2 --- Background --- p.8 / Chapter 2.1 --- Lumped Elements Baluns --- p.8 / Chapter 2.1.1 --- λ/4 Transmission Line Equivalent Circuit Model --- p.10 / Chapter 2.1.2 --- 3λ/4 Transmission Line Equivalent Circuit Model --- p.14 / Chapter 2.1.3 --- Design Procedure of Lumped Element Balun --- p.18 / Chapter 2.2 --- Distributed Baluns --- p.29 / Chapter 2.2.1 --- Coupled Line --- p.29 / Chapter 2.2.2 --- Marchand Balun --- p.34 / Chapter 2.2.3 --- Stepped Impedance Balun --- p.38 / Chapter 2.2.4 --- New Structure Coupled-Line Balun --- p.53 / Chapter 2.3 --- Planar Balun --- p.63 / Chapter 2.4 --- Advantage and Disadvantage of Existed Balun Design --- p.69 / Chapter Chapter 3 --- Size Reduction Method of Coupled Lines --- p.71 / Chapter 3.1 --- New Proposed Method of Coupled Line Size Reduction --- p.71 / Chapter 3.2 --- Simulation Result of Capacitor Loaded Coupled Line --- p.77 / Chapter Chapter 4 --- Capacitor Loaded Coupled Line Balun --- p.82 / Chapter 4.1 --- Simulation Result of Capacitor Loaded Coupled-Line Balun --- p.82 / Chapter Chapter 5 --- Design of New Coupled Line Balun Using Capacitor Loaded Coupled Lines --- p.88 / Chapter 5.1 --- Design Specifications of Reduced Coupled-Line Balun --- p.89 / Chapter 5.2 --- Design of Capacitors --- p.90 / Chapter 5.3 --- Layout and Simulation Result of 2.4GHZ LTCC Capacitor Loaded Coupled-Line Balun --- p.96 / Chapter Chapter 6 --- Conclusion and Future Work --- p.104 / References --- p.106 / Author's Publication --- p.109 / Appendix A Marchand Balun --- p.110 / Appendix B Reconstruction of S-Matrix for a 3-Port Measurement at Only Two-Ports --- p.117 / Appendix C Renormalization of Balun S-Matrix with Load Termination Z1 from S-Matrix with Load Termination Z0 --- p.120 / Appendix D Sensitivity analysis for capacitor loaded coupled line balun --- p.122

Miniaturization of electronic products due to the current trend in the electronics industry has led to the integration of components within the chip and package. Traditionally, individual decoupling capacitors placed on the surface of the board or the package have been used to decouple active switching circuits. However, with an increase in the clock rates and its harmonics with technology nodes, decoupling has to be provided in the GHz range. Discrete decoupling capacitors are no longer effective in this region because of the increased inductive effects of the current paths of the capacitors, which limits its effectiveness in the tens of MHz range. The use of embedded individual thick film capacitors within the package is a feasible solution for decoupling core logic above 100 MHz. They overcome the limitations of SMDs (Surface Mount Discretes), primarily in decoupling active circuits in the mid-frequency band. Inclusion of embedded planar capacitors in the board stack up have shown improvements in the overall impedance profile and have shown to exhibit better noise performance. The main contributor to the superior performance is the reduced inductive effects of the power-ground planes because of the thinner dielectrics of the embedded capacitor. The modeling, measurement and characterization of embedded decoupling capacitors in the design of PDNs (Power Distribution Networks) has been investigated in this thesis.

With the advantages of MOS monolithic technology in mind, Switched-Capacitor (SC) filter design and simulation are studied in this research. For SC circuit design, Shunt SC, bilinear, and LDI z-Transform methods are discussed. A practical design example, together with its circuit implementation, is used to check both design and simulation behaviors. For SC circuit simulation, certain methods are analyzed to compare with the Four-Port Method, from which a proposed method, STAMP, is derived. STAMP improves on the large computation time and storage space problems of other well-known programs. It has the capability of being expanded using some of the routines which are appended.

Since metal-oxide-semiconductor (MOS) devices have been adopted into integrated circuits, the endless demands for higher performance and lower power consumption have been a primary challenge and a technology-driver in the semiconductor electronics. The invention of complementary MOS (CMOS) technology in the 1980s, and the introduction of voltage and physical dimension scaling in the 1990s would be good examples to keep up with the everlasting demands. In the 2000s, technology continuously evolves and seeks for more power efficiency ways such as high-k dielectrics, metal gate electrodes, strained substrates, and high mobility channel materials. As a gate dielectric, silicon dioxide (SiO₂), most widely used in CMOS integrated circuits, has many prominent advantages, including a high quality interface (e.g. Dit ~ low 1010 cm-2eV-1), a good thermal stability in contact with silicon (Si), a large energy bandgap and the large energy band offsets in reference to Si, and a high quality dielectric itself. As the thickness of SiO₂ keeps shrinking, however, SiO₂ is facing its physical limitations from the viewpoint of gate dielectric leakage currents and reliability requirements. High-k dielectric materials have attracted extensive attention in the last decade due to their great potential for maintaining further down-scaling in equivalent oxide thickness (EOT) and a low dielectric leakage current. HfO₂ has been considered as one of the most promising candidates because of a high dielectric constant (k ~ 20-25), a large energy band gap (~ 6 eV) and the large band offsets (> 1.5 eV), and a good thermal stability. To enhance carrier mobility, strained substrates and high mobility channel materials have attracted a great deal of attention, thus III-V compound semiconductor substrates have emerged as one of possible candidates, in spite of several technical barriers, being believed as barriers so far. The absence of high quality and thermodynamically stable native oxide, like SiO₂ on Si, has been one such hurdle to implement MOS systems on III-V substrates. However, recently, there have been a number of remarkable improvements on MOS applications on them, inspiring more vigorous research activities. In this research, HfO2-based MOS capacitors and metal-oxidesemiconductor field effect transistors (MOSFETs) with a thin germanium (Ge) interfacial passivation layer (IPL) on III-V compound substrates were investigated. It was found that a thin Ge IPL could effectively passivate the surface of III-V substrate, consequently providing a high quality interface and an excellent gate oxide scalability. N-channel MOSFETs on GaAs, InGaAs, and InP substrates were successfully demonstrated and a minimum EOT of ~ 9 Å from MOS capacitors was achieved. This research has begun with GaAs substrate, and then expanded to InGaAs, InP, InAs, and InSb substrates, which eventually helped to understand the role of a Ge IPL and to guide future research direction. Overall, MOS devices on III-V substrates with an HfO₂ gate dielectric and a Ge IPL have demonstrated feasibility and potential for further investigations. / text

Carbon nanotubes (CNTs) have become a popular area of materials science research due to their outstanding material properties coupled with their small size. CNTs are expected to be included in a wide variety of applications and devices in the near future. Among these devices which are nearing mass production are electrochemical double layer (ECDL) supercapacitors. The current methods to produce CNTs are numerous, with each synthesis variable resulting in changes in the physical properties of the CNT. A wide array of studies have focused on the effects of specific synthesis conditions. This research expands on earlier work done using bulk nickel catalyst, alumina supported iron catalyst, and standard chemical vapor deposition (CVD) synthesis methods. This work also investigates the effect of an applied voltage to the CVD chamber during synthesis on the physical nature of the CNTs produced. In addition, the work analyzes a novel nickel catalyst system, and the CNTs produced using this catalyst. The results of the effects of synthesis conditions on resultant CNTs are included. Additionally, CNT based ECDL supercapacitors were manufactured and tested. Scanning electron microscope (SEM) analysis reveals that catalyst choice, catalyst thickness, synthesis temperature, and applied voltage have different results on CNT dimensions. Nanotube diameter distribution and average diameter data demonstrate the effect of each synthesis condition. Additionally, the concept of an alignment parameter is introduced in order to quantify the effect of an electric field on CNT alignment. CNT based ECDL supercapacitors testing reveals that CNTs work well as an active material when a higher purity is achieved. The molarity of the electrolyte also has an effect on the performance of CNT based ECDL supercapacitors. On the basis of this research, we conclude that CNT physical dimensions can be moderately controlled based on the choice of synthesis conditions. Also, the novel nickel catalyst system investigated in this research has potential to produce bulk quantities of CNT under specific conditions. Finally, purified CNTs are recommended as a suitable active material for ECDL supercapacitors.

Indiana University-Purdue University Indianapolis (IUPUI) / This research proposes state-of-the-art multilevel converter topologies and their modulation strategies, the implementation of a conventional flying-capacitor converter topology up to four-level, and a new four-level flying-capacitor H-Bridge converter confi guration. The three phase version of this proposed four-level flying-capacitor H-Bridge converter is given as well in this study. The highlighted advantages of the proposed converter are as following: (1) the same blocking voltage for all switches employed in the con figuration, (2) no capacitor midpoint connection is needed, (3) reduced number of passive elements as compared to the conventional solution, (4) reduced total dc source value by comparison with the conventional topology. The proposed four-level capacitor-clamped H-Bridge converter can be utilized as a multilevel inverter application in an electri fied railway system, or in hybrid electric vehicles. In addition to the implementation of the proposed topology in this research, its experimental setup has been designed to validate the simulation results of the given converter topologies.