This thesis comprises two parts : the first one is the design and implementation of FlexRay automotive communication system physical layer; the second part is the design of a high speed pipelined tree-structured carry lookahead adder (CLA). The first part of this thesis is to introduce the physical layer specification of FlexRay automotive communication system. Then, it is realized in an SOC by a typical 0.18 um CMOS process. The second topic is to propose a novel CANT logic. By the CANT logic, a pipelined tree-structured carry lookahead adder is designed and implemented. The dynamic bulk biasing technique is utilized to increase the switching speed of inverting circuits such that the delays of the inverting and non-inverting circuit is very close. The proposed architecture can be easily expanded to long data words CLA. Post-layout simulations reveal that the 32-bit CLA using the proposed CANT logic can operate up to 7.2 GHz by using the UMC 90 nm process.

This thesis includes two topics. The first topic is a low power design of 8-bit ANT-based pipelining CLA. The second one is a small digital to analog converter (DAC) used in an implantable neural stimulator. An ANT-based low-power 8-bit pipelining carry-lookahead adder (CLA) using two-phase all-N-transistor (ANT) blocks which are arranged in a PLA design style with power-aware pipelining is presented. The pull-up charging and pull-down discharging of the transistor arrays of the PLA are accelerated by two feedback MOS transistors between the evaluation NMOS blocks and the outputs. Both the added power-aware clock control circuit and clock generation circuit detecting data transition take advantage of shutting down the processing stages given identical inputs in two consecutive operations by keeping high clock level. The design keeps the advantage of high speed while having the effect of low power dissipation. The implantable neural stimulator assists patients to reconstruct transmission paths of neural signals by current stimulation. The proposed small DAC not only decreases the chip area and power dissipation by reducing transistor count, but also improves the linearity with higher current output performance. All of measured performances of the proposed DAC make the chip worthy of being implemented in a field application.

Abstract The tremendous progress in all aspects of signal processing technology has naturally been accompanied by a corresponding development of arithmetic techniques to provide high-speed operations at reasonable complexity. In the past, many architectural design efforts have focused on maximizing performance for frequently executed simple arithmetic operations such as addition and multiplication while left other rarely used operations ignored. In this dissertation, we firstly propose two design approaches for 64-b carry-lookahead adders (CLA) using a two-phase clocking dynamic CMOS logic since fast adders are the key elements in many digital circuits. Secondly, we place emphasis on the inner product operation since it is one of the most frequently used mathematical operations in the computation of digital neural networks. A ratioed 3-2 compressor is also presented to resolve several physical design problems that are not fully considered or implemented in previous research works. Finally we propose several fast 64b/32b integer dividers because the integer division is unavoidable in many important signal-processing applications.