The main purpose of this research is to analyze and improve manufacturing process of chip resistor . To startup research by collecting chip resistor related thesises and patents, and as a result, discover most research paper are focused on structure and material, seldom found information related to manufacturing and process. As a matter of fact, manufacturing and process is crucial for mass production. Continued by analyzing chip resistor's structure and manufacture process, use defect sample collected from current manufacturing. Apply functional analysis to explore manufacturing system and environment. Base on analysis on functional structure and the limitation of structure, propose three ways of changing the processing sequence which provide improvement. In one case, after been trail run, it can actually reduce defect of manufacturing and speedup the operation flow. List designing and operating operable of detail stage, according to equipment jig and product dimension explore approach, choose a approach optimum what it raise efficiency and improve defect of chip resistor. Analyze resistance distribution and reliability test after test batch, confirm chip resistor¡¦s function and specification. Analyze defect rate of production ramp-up last. Result of study, provide optimum procedure could be reduce defect rate. Whole process of study, compare defect rate of current and optimum approach, optimum approach could be reduce defect rate from 8.5¢H to 1.3¢H.

Spacecloth design and development is vital and crucial in Radar Absorbing Materials (RAM) for achieving Low Observability in an Aircraft or an Unmanned Air Vehicle(UAV). The RAM design translates into the spacecloth design. The spacecloths form the constituent layers in a broadband Jaumann absorber in which case they have to be designed for various values of surface resistivity. The design specifications of spacecloth(s) in RAMS is well understood and documented in literature. But the design of spacecloth hitherto, has been the domain of materials' scientists wherein the specified properties of the spacecloth are achieved by an iterative, trial and error process, by mixing various constituents in different proportions to get the design specified surface resistivity in the final end-product. In an effort to bridge this gap, a novel spacecloth for RAM applications is proposed in the thesis. It is proposed that a repetitive geometrical grid network of chip resistors simulates spacecloth. The sheet resistivity of the spacecloth is derived by analyzing various geometries like square, rectangle, triangle and hexagonal grids. The transmission and reflection loss for the chip resistor spacecloth is derived. The design of chip resistor spacecloths for operation at S and C bands is given followed by experimental verification using waveguide simulator experiments. Numerical study of multilayer RAM has been carried out with exponential taper variation of surface resistivities for constituent spacecloth layers and design curves are given for multilayer RAM both for normal and oblique incidence for TE and TM polarizations.