L’étude présentée s’inscrit dans le cadre général de l’amélioration de la fiabilité mécanique des composants électroniques. Les composants de type WL-CSP (Wafer-Level Chip-Scale Package : boîtier aux dimensions comparables à celles de la puce) sont couramment utilisés dans les appareils nomades (par exemple les téléphones) et assurent de nombreuses fonctions. La tenue dans le temps de ces appareils passe par l’allongement de la durée de vie de leurs éléments. Ce sujet est une problématique complexe car la structure des composants peut varier selon les technologies employées et nécessite des essais spécifiques, qui consomment beaucoup de temps et de ressources.Un modèle numérique est développé afin d’accélérer le développement des boîtiers de ces composants et d’optimiser les ressources disponibles. Des essais de fiabilité sont menés sur le test de chute et un banc d’essai de flexion est mis en place. Les résultats de ces essais permettent de valider la simulation numérique et de mettre au point un modèle de fatigue.D’autre part, une campagne de caractérisation des matériaux permet de déterminer les propriétés mécaniques de la structure étudiée. La caractérisation concerne notamment les couches minces pour lesquelles les propriétés mécaniques sont fortement dépendantes de leurs conditions de dépôts.Ces éléments sont incorporés dans un modèle numérique incluant un certain nombre d’hypothèses. Le modèle est confronté à l’expérience pour déterminer les constantes d’un modèle de fatigue. Ensuite, la simulation et le modèle de fatigue sont utilisés conjointement pour évaluer l’influence de paramètres géométriques et matériaux sur la fiabilité des composants de type WL-CSP. / The work described in this report is related to the mechanical improvement of electronicdevices mechanical reliability. WL-CSP (Wafer-Level Chip-Scale Package) components are widely used in handheld devices and run many functions. The longevity increase of such adevice necessarily requires progresses in its components reliability. This subject is complexas the component structure can vary depending on the employed technologies. So, it requires time and ressources.A numerical model is developed to enhance the packages development as well as available resources. Reliability tests are performed on the drop-test bench and a bend-testbench is designed. These tests provide results to validate the numerical results and to establish a fatigue model.Aside from these tests, the component materials are characterized to determine the studied structure properties. It specifically concerns the thin layers for which mechanical properties strongly depends on the deposition process. All of this is incorporated in a numerical model which includes hypotheses. The model is compared with the experiments to determine fatigue model constants. Then, modeling and experiments are used together to evaluate material and geometrical parameters influence.

The Wafer Level Chip Scale Package (WLCSP) is gaining popularity for its performance and ability to meet the miniaturization requirements of portable consumer electronics, such as cell phones. For the industry of electronic package, the package life of electronic products is deemed as the essential consideration in the operation period. In practice, electronic products are usually damaged due to a harsh mechanical impact, such as drop and bending. The solder interconnections provide not only the electronic path between electric components and printing circuit board, but also the mechanical support of components on the printing circuit board, so that the reliability of solder interconnection becomes an essential consideration for a package. In the thesis several parameters, including redistribution layer (RDL) material and thickness, passivation material and thickness, under-bump metallization (UBM) structure factors are discussed. A variety of WLCSP structures are investigated for solder joint reliability performance. In addition to the fatigue lives of the test vehicle, locations and modes of fractured solder joints were observed. It was found that wafer level packaging structure under drop clearly related with the characteristic life. The weakest point of solder ball was intermetallic compound (IMC), and wafer level packaging structure was the crack into the second passivation layer and UBM interface of the corner. WLCSP under temperature cycling test was done and observed the fracture only occurred at the solder ball near the package.

Double cantilever beam (DCB) specimens with distinct intermetallic microstructures and different geometries were fractured under different mode ratios of loading, ψ, to obtain critical strain energy release rate, Jc. The strain energy release rate at crack initiation, Jci, increased with phase angle, ψ, but remained unaffected by the joint geometry. However, the steady-state energy release rate, Jcs, increased with the solder layer thickness. Also, both the Jci and Jcs decreased with the thickness of the intermetallic compound layer. Next, mode I and mixed-mode fracture tests were performed on discrete (l=2 mm and l=5 mm) solder joints arranged in a linear array between two copper bars to evaluate the J = Jci (ψ) failure criteria using finite element analysis. Failure loads of both the discrete joints and the joints in commercial electronic assemblies were predicted reasonably well using the Jci from the continuous DCBs. In addition, the mode-I fracture of the discrete joints was simulated with a cohesive zone model which predicted reasonably well not only the fracture loads but also the overall load-displacement behavior of the specimen. Additionally, the Jci calculated from FEA were verified estimated from measured crack opening displacements in both the continuous and discrete joints. Finally, the pad-crater fracture mode of solder joints was characterized in terms of the Jci measured at various mode ratios, ψ. Specimens were prepared from lead-free chip scale package-PCB assemblies and fractured at low and high loading rates in various bending configurations to generate a range of mode ratios. The specimens tested at low loading rates all failed by pad cratering, while the ones tested at higher loading rates fractured in the brittle intermetallic layer of the solder. The Jci of pad cratering increased with the phase angle, ψ, but was independent of surface finish and reflow profile. The generality of the J =Jci(ψ) failure criterion to predict pad cratering fracture was then demonstrated by predicting the fracture loads of single lap-shear specimens made from the same assemblies.

Double cantilever beam (DCB) specimens with distinct intermetallic microstructures and different geometries were fractured under different mode ratios of loading, ψ, to obtain critical strain energy release rate, Jc. The strain energy release rate at crack initiation, Jci, increased with phase angle, ψ, but remained unaffected by the joint geometry. However, the steady-state energy release rate, Jcs, increased with the solder layer thickness. Also, both the Jci and Jcs decreased with the thickness of the intermetallic compound layer. Next, mode I and mixed-mode fracture tests were performed on discrete (l=2 mm and l=5 mm) solder joints arranged in a linear array between two copper bars to evaluate the J = Jci (ψ) failure criteria using finite element analysis. Failure loads of both the discrete joints and the joints in commercial electronic assemblies were predicted reasonably well using the Jci from the continuous DCBs. In addition, the mode-I fracture of the discrete joints was simulated with a cohesive zone model which predicted reasonably well not only the fracture loads but also the overall load-displacement behavior of the specimen. Additionally, the Jci calculated from FEA were verified estimated from measured crack opening displacements in both the continuous and discrete joints. Finally, the pad-crater fracture mode of solder joints was characterized in terms of the Jci measured at various mode ratios, ψ. Specimens were prepared from lead-free chip scale package-PCB assemblies and fractured at low and high loading rates in various bending configurations to generate a range of mode ratios. The specimens tested at low loading rates all failed by pad cratering, while the ones tested at higher loading rates fractured in the brittle intermetallic layer of the solder. The Jci of pad cratering increased with the phase angle, ψ, but was independent of surface finish and reflow profile. The generality of the J =Jci(ψ) failure criterion to predict pad cratering fracture was then demonstrated by predicting the fracture loads of single lap-shear specimens made from the same assemblies.