Multiple-input multiple-output (MIMO) wireless technology is an emerging cost- effective approach to offer multiple-fold capacity improvement relative to the conven- tional single-antenna systems. To achieve the capacities of MIMO channels, MIMO bit-interleaved-coded-modulation (BICM) systems with iterative detection and decod- ing (IDD) are studied in this thesis. The research for this dissertation is conducted based on the iterative receivers with convolutional codes and turbo codes. A variety of MIMO detectors, such as a maximum a posteriori probability (MAP) detector, a list sphere detector (LSD) and a parallel interference canceller (PIC) together with a decision statistic combiner (DSC), are studied. The performance of these iterative receivers is investigated via bounding techniques or Monte-Carlos simulations. Moreover, the computational complexities of the components are quantified and compared. The convergence behaviors of the iterative receivers are analyzed via variance trans- fer (VTR) functions and variance exchange graphs (VEGs). The analysis of conver- gence behavior facilitates the finding of components with good matching. For a fast fading channel, we show that the &quotwaterfall region&quot of an iterative receiver can be predicted by VEG. For a slow fading channel, it is shown that the performance of an iterative receiver is essentially limited by the early interception ratio (ECR) which is obtained via simulations. After the transfer properties of the detectors are unveiled, a detection switching (DSW) methodology is proposed and the switching criterion based on cross entropy (CE) is derived. By employing DSW, the performance of an iterative receiver with a list sphere detector (LSD) of a small list size is considerably improved. It is shown that the iterative receiver achieves a performance very close to that with a maximum a posteriori probability (MAP) detector but with a significantly reduced complexity. For an iterative receiver with more than two components, various iteration sched- ules are explored. The schedules are applied in an iterative receiver with PIC-DSC. It is shown that the iterative receiver with a periodic scheduling outperforms that with the conventional scheduling at the same level of complexity.

Thesis (Ph.D.)--McMaster University, 2006. / Supervisor: Timothy N. Davidson. Includes bibliographical references (p. 163-172).

Bibliography: p.103-104. / Contract DA36-039-AMC-03200(E).

Bibliography: p. 76-77. / Contract AF 19(628)-500

References: p.41. / Contract DA36-039-AMC-03200(E). Grant DA-SIG-36-039-61-G14. Grant GP-2495. Grant MH-04737-04. Grant NsG-496.

Russell R. Pfeiffer. / Issued also as a thesis, M.I.T. Dept. of Electrical Engineering, May 20, 1960. "December 4, 1960." / Bibliography; p. 32. / Dept. of the Army Task 3-99-20-001 Project No. 3-99-10-022.

Barney Reiffen. / "August 12, 1960." Issued also as thesis, M.I.T. Dept. of Electrical Engineering, August 22, 1960. / Bibliography: leaf 98. / Army Signal Corps Contract DA36-039-sc-78108. Dept. of the Army Task 3-99-20-001 and Project 3-99-00-000.

by Roger J. Camrass & Robert G. Gallager. / Bibliography: p. 11. / "Revised January 1977." / National Science Foundation Grant NSF/ENG76-24447

D.G. Wimpey, T.L. Johnson, M.E. Kaliski. / Bibliography: p. 6. / "April, 1981." / U.S. Air Force Office of Scientific Research contract F49620-80-C-0002

Electronic signal processing techniques have assumed a prominent role in the design of fibre-optic communication systems. However, state-of-the-art systems operate at per-channel data rates of 100 Gb/s, which constrains the class of communication algorithms that can be practically implemented. Relative to LDPC-like codes, product-like codes with syndrome-based decoding have decoder dataflow requirements that are smaller by more than two orders of magnitude, which strongly motivates the search for powerful product-like codes. This thesis presents a new class of high-rate binary error-correcting codes, staircase codes, whose construction combines ideas from convolutional and block coding. A G.709-compliant staircase code is proposed, and FPGA-based simulation results show that performance within 0.5 dB of the Shannon Limit is attained for bit-error-rates below 1E-15. An error-floor analysis technique is presented, and the G.709-compliant staircase code is shown to have an error floor below 1E-20. Using staircase codes, a pragmatic approach for coded modulation in fibre-optic communication systems is presented that provides reliable communications to within 1 bit/s/Hz of the capacity of a QAM-modulated system modeled via the generalized non-linear Schrodinger equation. A system model for a real-world DQPSK receiver with correlated bit-errors is presented, along with an analysis technique to estimate the resulting error floor for the G.709- compliant staircase code. By applying a time-varying pseudorandom interleaver of size 2040 to the output of the encoder, the error floor of the resulting system is shown to be less than 1E-20.