University, Diss., 1996--Saarbrücken.

<p>MATLAB to C code translation is of increasing interest for science and industry. In</p><p>detail two MATLAB to C compilers denoted as Matlab to C Synthesis (MCS) and</p><p>Embedded MATLAB C (EMLC) have been studied. Three aspects of automatic code</p><p>generation have been studied; 1) generation of reference code; 2) target code generation;</p><p>3) floating-to-fixed-point conversion. The benchmark code used aimed to cover</p><p>simple up to more complex code by being viewed from a theoretical as well as practical perspective. A fixed-point filter implementation is demonstrated. EMLC and MCS</p><p>offer several fixed-point design tools. MCS provides a better support for C algorithm</p><p>reference generation, by covering a larger set of the MATLAB language as such. More</p><p>suitable for direct target implementation is code generated from EMLC. As a result</p><p>of the need to guarantee that the EMLC generated C-code allocates memory only</p><p>statically, MATLAB becomes more constraint by EMLC. Functional correctness was</p><p>generally achieved for each automatic translation.</p>

To the general purpose microprocessors, we often need to change microprocessors¡¦ hardware architecture because of customized purpose. But already existing application program is incompatible to the new hardware architecture, and increase the product¡¦s development period. In this thesis, we discuss the modification of two kinds of hardware architecture, include new instruction set extension and change the size of datapath to deal with specific application. To the former, our laboratory develop a 32-bit microprocessor SYS32-TM, increase MME instruction set to deal with multimedia application. The latter, based on Thumb instruction set , we develop 16-bit microprocessor SYS16-TM, we modify its¡¦ datapath from 32-bit to 16-bit, we will show how to let already existing application program can execute on the new hardware architecture. In SYS32-TM, we use the way of inline assembly to embedded MME instruction set in C source code, we have to modify the assembler, define and parse the MME instruction set, so the assembler can recognize it. In SYS16-TM, we have sign extension and address offset problems, we have to modify the compiler backend¡¦s machine description to solve the sign extension and address offset instruction set behavior, and modify the library. To build SYS16-TM software environment, we have to set C Run Time Environment in Thumb mode, not support exchange between ARM mode and Thumb mode, and write the correct linker script, to set the program start address in 0x0000, to solve ARM¡¦s initial program start address in 0x8000. As a result, In SYS32-TM, we use assembler to identify the MME instruction set can embedded in existing C source code. In SYS16-TM, we execute the testbench include sorts, Hanoi, Fibonacci number etc, and use simulator to verify its¡¦ correctness.

For the past several decades, parallel processing has become an important research subject in the computer science area. According to the statistics, in executing a numerical program, most of time is spent on the loops. If we can use the technique of loop restructuring in the parallelizing compiler such that the conventional sequential program can be executed by exploiting the characteristics of vector machine or parallel machine, the execution efficiency will be greatly improved. In the parallelizing compiler, data dependence analysis is very important because it provides the information for loop restructuring. Data dependence analysis is necessary in order to determine whether a loop can be vectorized or parallelized. It analyzes whether the same array element or variable will be accessed more than once in a loop (e.g. access the same memory location more than once in loop execution). In the recent years, the researches on parallelizing compiler are considerable. But, data dependence analysis is still a bottleneck. There are many data dependence test such as Banerjee Test, test, Omega Test, I Test, Power Test, ... and so on, which have been used in the design of parallelizing compiler. In the thesis, we will propose a novel exact data dependence test method called Interval Reduced test (IR test). This method reduces the integer boundary of each constraint variable by repeatedly projection. When the effective region of a variable is reduced to be empty, the constraint containing this variable has no integer solution and the memory accesses under this constraint are therefore independent. The IR test is only suitable for the loops in which the loop bounds are rectangular, triangular, or unknown at compiling-time in some limited condition. To enhance the data dependence analysis capability of the IR test, we proposed the Extension-IR test in this thesis to extend the dependence testing range of one-dimensional array references to linear subscripts with variable bounds under any given direction vector. The Extension-IR test can solve in effective polynomial time. When array subscripts are non-linear expressions or too complex to analyze by the existing data dependence testing schemes, we devise a new parallelization algorithm called non-linear array subscripts test (NLA test) to deal with. The iterations subject to loop-carried dependence are scheduled into different wavefronts, while the iterations with no loop-carried dependence are assigned into the same wavefront. Based on the wavefront information, the original loop is transformed into parallel code for execution at run-time. Loop interchange is an important restructuring technique for supporting vectorization and parallelization. In this thesis, we proposed a technique, which can determine efficiently, whether loops can be interchanged between two non-adjacent loops on perfect nested loop or some imperfectly nested loop. A method for determining whether two arbitrary levels in perfectly nested loops, which contain IF and GOTO statements, can be interchanged is also presented in this thesis.

MATLAB to C code translation is of increasing interest for science and industry. In detail two MATLAB to C compilers denoted as Matlab to C Synthesis (MCS) and Embedded MATLAB C (EMLC) have been studied. Three aspects of automatic code generation have been studied; 1) generation of reference code; 2) target code generation; 3) floating-to-fixed-point conversion. The benchmark code used aimed to cover simple up to more complex code by being viewed from a theoretical as well as practical perspective. A fixed-point filter implementation is demonstrated. EMLC and MCS offer several fixed-point design tools. MCS provides a better support for C algorithm reference generation, by covering a larger set of the MATLAB language as such. More suitable for direct target implementation is code generated from EMLC. As a result of the need to guarantee that the EMLC generated C-code allocates memory only statically, MATLAB becomes more constraint by EMLC. Functional correctness was generally achieved for each automatic translation.

Stuttgart, Univ., Fakultät Informatik, Diplomarb., 1997.

Stuttgart, Univ., Fakultät Informatik, Diplomarb., 1998.

Ulm, Univ., Diss., 2002.

abstract: The holy grail of computer hardware across all market segments has been to sustain performance improvement at the same pace as silicon technology scales. As the technology scales and the size of transistors shrinks, the power consumption and energy usage per transistor decrease. On the other hand, the transistor density increases significantly by technology scaling. Due to technology factors, the reduction in power consumption per transistor is not sufficient to offset the increase in power consumption per unit area. Therefore, to improve performance, increasing energy-efficiency must be addressed at all design levels from circuit level to application and algorithm levels. At architectural level, one promising approach is to populate the system with hardware accelerators each optimized for a specific task. One drawback of hardware accelerators is that they are not programmable. Therefore, their utilization can be low as they perform one specific function. Using software programmable accelerators is an alternative approach to achieve high energy-efficiency and programmability. Due to intrinsic characteristics of software accelerators, they can exploit both instruction level parallelism and data level parallelism. Coarse-Grained Reconfigurable Architecture (CGRA) is a software programmable accelerator consists of a number of word-level functional units. Motivated by promising characteristics of software programmable accelerators, the potentials of CGRAs in future computing platforms is studied and an end-to-end CGRA research framework is developed. This framework consists of three different aspects: CGRA architectural design, integration in a computing system, and CGRA compiler. First, the design and implementation of a CGRA and its instruction set is presented. This design is then modeled in a cycle accurate system simulator. The simulation platform enables us to investigate several problems associated with a CGRA when it is deployed as an accelerator in a computing system. Next, the problem of mapping a compute intensive region of a program to CGRAs is formulated. From this formulation, several efficient algorithms are developed which effectively utilize CGRA scarce resources very well to minimize the running time of input applications. Finally, these mapping algorithms are integrated in a compiler framework to construct a compiler for CGRA / Dissertation/Thesis / Doctoral Dissertation Computer Science 2015

<p> The emphasis of my essay are on the description of the language syntax, listing the functions of the major routines, with emphasis put on the use of the current operator - next operator (CO - NO) tables, and a discussion on the code generated by each statement.</p> / Thesis / Master of Science (MSc)