A CMOS implementation of a True-Q Flip Flop is presented. It can perform either as an asynchronous storage element in micropipelines or a part of the synchronizer. It is capable of double-edge triggering which latches data at both the rising and the trailing edges. It is also free of the metastability state problem. Some analog and digital circuits are incorporated with a true double-edge triggered Flip Flop (DETFF) making it a True-Q Flip Flop. A True-Q Flip Flop outputs an acknowledge signal only after the Q and NQ are stabilized. Therefore, if the proceeding stages utilize this acknowledge signal as the triggering signal, then, the value of Q from the flip flop will not be received by the next stage if Q is in a metastable state. The number of transistors used in this implementation of True-Q flip flop is 90. Due to the overhead of circuit complexity, the time delay from Request to Acknowledge signal is 6.5ns. / Graduation date: 1995

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This thesis describes the analysis and comparison of Folded Source-Coupled Logic (FSCL) with standard static CMOS, cascode voltage-switch logic and differential split-level logic gates. The advantages of FSCL are low switching noise and high operating speed. The effect of voltage and device scaling on these topologies is evaluated in terms of average delay, power dissipation at maximum frequency, power-delay-product and current spike noise. Several two-summand adders are designed and simulated using MOSIS 1-μm CMOS process parameters and evaluations are performed in terms of area, delay, noise and power dissipation. / Graduation date: 1994

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在過去的幾十年中，無線通信已經歷了顯著的發展，並成為日常生活中必不可少的一部分。隨著對可移動便攜式電子設備的需求不斷增加，功耗已经成為射頻前端電路設計的一個最關鍵參數。在便攜式無線消費類電子中，頻率綜合器在收发机设计中提供本地振盪器（LO），它又是一個高功耗的子系統之一。降低頻率綜合器的功耗將會直接影响電池的使用時間。 / 為了驗證進來新型的低功耗技术，本文基於低成本的0.18微米三阱CMOS工藝，設計並實現了三個不同的電路模塊和一個頻率綜合器系統。第一個設計是一個低壓正交壓控振盪器(QVCO)和除肆分頻器的電流復用電路。在沒有損耗電壓餘量的情況下，兩個高頻模塊通過電流復用的方式，從而降低了功耗。測試結果顯示當電源電壓為1.3V ，電流消耗電流為2.7毫安。在2.2 GHz載波附近1MHz頻偏位置上的相位噪聲為 -114 dBc/Hz。第二個設計是應用於SDR的變壓器和電流復用的壓控振盪器/分頻器的電路。該電路通過調整偏置電壓，僅用一個分頻器就可以實現可變分頻比（2，3，…,9）的功能。實驗結果表明，分頻器的輸出頻率範圍從0.58至3.11 GHz，在5.72 GHz載波附近1MHz頻偏位置上的相位噪聲為-112.5 dBc / Hz，電源電壓為1.8V時，電流為4.7mA。第三個設計是應用於UWB的變壓器和電流復用的QVCO / SSBM電路。這個全新的結構電路面積為0.8平方毫米，在1.6V電源電壓下，消耗功耗約為11 mA。測量結果表明，帶外雜散抑制小於43dBc，頻率偏移1MHz位置處的相位噪聲小於-112 dBc/Hz。最後一個設計是應用於 MB-OFDM UWB的頻率綜合器。這個新結構只用了一個電感在不犧牲主要性能的情況下，可以實現小的芯片尺寸和低的功耗。測試結果全部基於UWB的頻段，相位噪聲為-119 dBc/Hz@10 MHz，電源電壓1.2 V，總電流消耗為24.7mA。 / Over the past decades, wireless communication has experienced a remarkable development and become an essential part of daily life. With the rapid increasing demand for mobile and portable electronic devices, the power dissipation has become one of the most critical design parameters, especially for RF front-ends. In portable wireless consumer electronics, the RF frequency synthesizer is one of the most power-consuming subsystems, which serves as local oscillator (LO) in transceiver design. Any power saving in frequency synthesizer will directly affect the running time of battery. / To demonstrate recent innovation in low power techniques, three different circuit blocks and one frequency synthesizer have been developed and fabricated in low-cost 0.18μm triple-well CMOS process. The first design is a low-voltage current reused quadrature VCO and divider-by-4 frequency divider circuit. By the novel sharing of transistors between the two high frequency blocks, the power consumption of the overall design can be reduced with little penalty on voltage headroom. Experimental results show a phase noise level of -114 dBc/Hz at 1 MHz offset from 2.2 GHz carrier and consumes 2.7 mA from a 1.3V power supply. The second design is a transformer-based current reused VCO/ILFD circuits for SDR application. By the adoption of bias tuning techniques, variable division ratios (2,3,…,9) can be achieved with a single divider circuit. Experimental results show an output frequency ranging from 0.58 to 3.11 GHz and a phase noise level of -112.5 dBc/Hz at 1 MHz offset from 5.72 GHz carrier, with a consumed current of 4.7 mA from a 1.8V power supply. The third design is a transformer-based current-reused QVCO/SSBM circuit for UWB application. The prototype is the first of its kind, while occupies a core area of 0.8 mm² and consumes roughly 11 mA from 1.6V power supply. Measurement results show that the out-of-band spurious rejection and phase noise at 1 MHz offset are better than 43 dBc and -112 dBc/Hz respectively. The final design is a frequency synthesizer for MB-OFDM UWB application. It uses a single inductor approach and novel system architecture to realize compact die size and low power consumption without sacrificing major performance. Experimental results show a phase noise level of -119 dBc/Hz@10 MHz offset for all UWB bands and consumes 24.7 mA from a 1.2 V power supply. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Li, Wei. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese. / Abstract --- p.i / Acknowledgement --- p.v / Table of Contents --- p.vi / List of Figures --- p.xi / List of Table --- p.xvi / Chapter CHAPTER 1 --- INTRODUCTION --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Outline of Dissertation --- p.3 / References --- p.5 / Chapter CHAPTER 2 --- A NOVEL LOW-VOLTAGE CURRENT REUSED, QUADRATURE VCO AND DIVIDE-BY-4 FREQUENCY DIVIDER --- p.6 / Chapter 2.1 --- Introduction --- p.6 / Chapter 2.2 --- Oscillation Principle of VCO --- p.9 / Chapter 2.3 --- Circuit Implementation --- p.14 / Chapter 2.3.1 --- Back-gate Coupled QVCO --- p.14 / Chapter 2.3.2 --- Divider-by-4 Frequency Divider --- p.20 / Chapter 2.3.3 --- Current Reuse QVCO and Frequency Divider --- p.24 / Chapter 2.3.3.1 --- Voltage Headroom --- p.25 / Chapter 2.3.3.2 --- Startup Condition --- p.26 / Chapter 2.3.3.3 --- Operating Range --- p.27 / Chapter 2.3.3.4 --- Phase Noise --- p.28 / Chapter 2.3.3.5 --- Transient Response --- p.30 / Chapter 2.4 --- Experimental Result --- p.31 / Chapter 2.4.1 --- Frequency Tuning Range --- p.32 / Chapter 2.4.2 --- Phase Noise --- p.33 / Chapter 2.4.3 --- Transient Response --- p.34 / Chapter 2.4.4 --- Performance Comparison --- p.34 / Chapter 2.5 --- Summary --- p.36 / Reference --- p.36 / Chapter CHAPTER 3 --- A TRANSFORMER BASED CURRENT REUSED VCO/ILFD CIRCUIT WITH VARIABLE DIVIDING RATIOS --- p.41 / Chapter 3.1 --- Introduction --- p.41 / Chapter 3.2 --- Transformer Design --- p.43 / Chapter 3.2.1 --- Ideal Transformer --- p.43 / Chapter 3.2.2 --- Transformer Tank --- p.45 / Chapter 3.3 --- Design of Current Reused VCO/ILFD --- p.49 / Chapter 3.3.1 --- Transformer Implement --- p.50 / Chapter 3.3.2 --- VCO Implement --- p.52 / Chapter 3.3.3 --- ILFD Implement --- p.54 / Chapter 3.4 --- Experiment Results --- p.60 / Chapter 3.4.1 --- Phase Noise --- p.61 / Chapter 3.4.2 --- Frequency Tuning Range --- p.62 / Chapter 3.4.3 --- Transient Response --- p.64 / Chapter 3.4.4 --- Performance Comparison --- p.65 / Chapter 3.5 --- Summary --- p.66 / Reference --- p.66 / Chapter CHAPTER --- 4 CURRENT REUSED QVCO/SSBM CIRCUIT FOR MB-OFDM UWB FREQUENCY SYNTHESIZER --- p.70 / Chapter 4.1 --- Introduction --- p.70 / Chapter 4.2 --- Proposed solution for UWB frequency synthesizer --- p.72 / Chapter 4.3 --- Bimodal Oscillation Phenomenon --- p.74 / Chapter 4.4 --- Design of Current Reused QVCO/SSBM Circuit --- p.81 / Chapter 4.4.1 --- Transformer Implementation --- p.82 / Chapter 4.4.2 --- QVCO Implementation --- p.85 / Chapter 4.4.3 --- SSBM Implementation --- p.88 / Chapter 4.5 --- Experimental Results --- p.89 / Chapter 4.5.1 --- Phase Noise --- p.91 / Chapter 4.5.2 --- Spur Suppression --- p.92 / Chapter 4.5.3 --- Performance Comparison --- p.93 / Chapter 4.6 --- Summary --- p.94 / Reference --- p.95 / Chapter CHAPTER 5 --- A SINGLE INDUCTOR APPROACH TO THE DESIGN OF LOW-VOLTAGE MB-OFDM UWB FREQUENCY SYNTHESIZER --- p.98 / Chapter 5.1 --- Introduction --- p.98 / Chapter 5.2 --- Frequency Synthesizer Background --- p.101 / Chapter 5.2.1 --- General Consideration --- p.101 / Chapter 5.2.1.1 --- Frequency Requirement --- p.102 / Chapter 5.2.1.2 --- Phase Noise --- p.103 / Chapter 5.2.1.3 --- Spurious Tones --- p.104 / Chapter 5.2.1.4 --- Switching Time --- p.105 / Chapter 5.2.2 --- Overview of MB-OFDM UWB Frequency Synthesizer --- p.105 / Chapter 5.3 --- Frequency Synthesizer System Design --- p.109 / Chapter 5.3.1 --- Proposed Frequency synthesizer Architecture --- p.109 / Chapter 5.3.2 --- Stability Analysis --- p.111 / Chapter 5.3.3 --- Phase Noise Contribution --- p.115 / Chapter 5.4 --- Circuit Implementation --- p.121 / Chapter 5.4.1 --- Current Reused Multiplier/SSBM --- p.121 / Chapter 5.4.2 --- 12-Phase Cross-coupled Ring VCO --- p.128 / Chapter 5.4.3 --- Regenerative Frequency Divider --- p.131 / Chapter 5.4.4 --- Tri-mode Phase Calibration Buffer --- p.132 / Chapter 5.4.5 --- Phase-Frequency Detector(PFD) --- p.134 / Chapter 5.4.6 --- Charge Pump --- p.135 / Chapter 5.4.7 --- CML Divider --- p.136 / Chapter 5.5 --- Experimental Result --- p.137 / Chapter 5.5.1 --- Frequency Tuning Range --- p.139 / Chapter 5.5.2 --- Phase Noise --- p.140 / Chapter 5.5.3 --- Spur Suppression --- p.141 / Chapter 5.5.4 --- Performance Comparison --- p.142 / Chapter 5.6 --- Summary --- p.143 / Reference --- p.143 / Chapter CHAPTER 6 --- CONCLUSIONS AND FUTURE WORKS --- p.147 / Chapter 6.1 --- Conclusions --- p.147 / Chapter 6.2 --- Future Works --- p.149 / List of Publication --- p.150

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

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Parallel optical interconnects (POI) have attracted a great deal of attention in the past two decades as the system bandwidth continues to increase. Optical interconnects are known to have more advantages than their electrical counterparts in many aspects such as crosstalk, bandwidth distance product, power consumption, and RC time delay. The parallelization of several optical links is also an effective method to increase the aggregate data rate while keeping the component count manageable and to reduce the unit cost of optics, electronics, and packaging at lower line rate. / Parallel optical transceiver modules running at several gigabits per second are commercially available nowadays. Parallel optical receivers are one of the key components of parallel interconnected systems. In this work, we describe how a low-power parallel CMOS preamplifier IC and a deskew IC have been designed and fabricated through the IBM 0.13mum CMOS technology. The performances of three different transimpedance amplifier (TIA) topologies are compared experimentally. The best of the three TIAs shows a differential gain of 56.2dBO, 2.6GHz bandwidth, and less than -16dBm sensitivity with a bit-error-rate (BER) less than 10-12. The TIA consumes 2.5mW of power from a 1.2V supply while the channel power is 22mW with a 400mV pp differential output swing. / A novel method of accurately measuring the crosstalk power penalty with an on-chip PRBS generator is proposed and its implementation is described. The use of an on-chip PRBS generator to drive the dummy channels eliminates the data pattern dependence between the aggressors and the victim. The inevitable channel skew associated with parallel channels can be removed by a phase-locked loop (PLL) based deskew method. We investigated the skew compensation range of this method theoretically and our experimental results confirm our conclusion. / Various practical design and test techniques such as photodiode modeling, AC coupling, low-pass filtering and continuous skew generation, and their implementations, are discussed and implemented in this thesis.

Thesis (M.S.)--University of Hawaii at Manoa, 2005. / Includes bibliographical references (leaves 95-98). / xii, 98 leaves, bound ill. 29 cm

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