Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003. / Includes bibliographical references (leaves 100-105). Also available in electronic version. Access restricted to campus users.

Thesis (M.S.)--Rochester Institute of Technology, 2005. / Typescript. Includes bibliographical references (leaves 84-86).

This study uses differential pass transistor methodology for implementing and evaluating Boolean functions. The main goal is investigation of CMOS and nMOS approaches in pass transistor logic design. Pass-transistor logic is most effective in the implementation of Boolean functions when the vectors are in the same format. It has been demonstrated that nMOS pass transistor logic driven by a control signal voltage above the V dd level offers a significant improvement in speed. nMOS pass transistorsalso offer less area consumption in comparison to the CMOS approach. The philosophy developed here has been used in the design of a program for the layout generation of pass transistor networks. This program has been applied to the design of a 4-to-1 multiplexer and an adder (sum and carry). The layout of the circuit sub-cell have been done using the program Magic, based on 3μ CMOS p-well technology.

Radio-frequency filters and oscillators are widely used in wireless communication and high-speed digital systems, and they are mostly built on passive integrated inductors, which occupy a relative large silicon area. This research attempted to implement filters and oscillators operating at 1-5 GHz using transistors only, to reduce the circuits’ area. The filters and oscillators are designed using active inductors, based on the gyrator principle; they are fabricated in standard digital CMOS technology to be compatible with logic circuits and further lower the cost. To obtain the highest operating frequency, only parasitic capacitors were used. Two new active-inductor circuits are derived from this research, labeled allNMOS and all-NMOS-II. The all-NMOS active inductor was used to design high-Q bandpass filters and oscillators, which were fabricated in TSMC’s 0.18-µm digital CMOS process. The highest center frequency measured was 5.7 GHz at 0.20-µm gate length and the maximum repeatably measured Q was 665. 2.4-GHz circuits were also designed and fabricated in 0.40-µm gate length. The all-NMOS-II circuit has superior linearity and signal fidelity, which are robust against process and temperature variations, due to its novel structure. It was used in signal drivers and will be fabricated in commercial products. Small-signal analysis was conducted for each of the active-inductor, filter and oscillator circuits, and the calculated performance matches those from simulations. The noise performance of the active inductor, active-inductor filter and oscillator was also analyzed and the calculated results agree with simulations. The difference between simulation and measured results is about 10% due to modeling and parasitic extraction error. The all-NMOS active-inductor circuit was granted a US patent. The US patent for all-NMOS-II circuit is pending. This research generated three conference papers and two journal papers.

Among the many efforts to improve the IC test process are tests that attempt to differentiate between healthy and defective or low reliability ICs by manipulating the operating conditions of the IC being tested. This thesis attempts to improve the common understanding of multiple and targeted temperature testing by evaluating work published on the subject to date and by presenting previously unpublished empirical observations. The empirical observations are made from SCAN and LBIST based MinVDD measurements, Static IDD measurements, as well as parametric measurements of transistor characteristics. The test vehicles used are 0.25μm and 0.18μm CMOS ASICs fabricated by LSI Logic. An IC’s performance is bound by a three dimensional space defined by VDD, frequency, and temperature. A model is presented to explain the boundaries of the performance region in terms of the ability of the IC’s constituent transistors to provide power and the Zero-Temperature-Coefficient (ZTC). Also, it is determined that multiple temperature testing can add new tests to current test suites to improve the resolution between healthy and defective ICs.

Today a growing number of applications in design engineering, production and environmental testing, and system service require specific analog waveforms and digital patterns. Such requirements are neither satisfactorily nor easily met by the use of standard function or single purpose, custom generators. Traditional methods of waveform generation suffer from undesirable complexity or mediocre performance and are otherwise limited. For the majority of arbitrary waveform generation applications, including medical engineering, modal analysis and electronic engineering, direct digital synthesis techniques are satisfactory. Direct digital synthesis, based generally on periodic retrieval of predetermined amplitude values, may be used to 2 generate such waveforms. Within the limits imposed by the system's maximum sample rate and the Nyquist criteria, any waveform may be produced using these techniques. The objective of this inquiry, within a particular set of constraints, is to extend the cost/performance envelope of direct digital synthesis techniques for the generation of arbitrary waveforms. Performance is enhanced, particularly in the areas of output bandwidth and signal purity.

Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2004. / Includes bibliographical references (p. 71-72).

Bandgap reference circuits are used in a host of analog, digital, and mixed-signal systems to establish an accurate voltage reference for the entire IC. The most used CMOS implementation for voltage references is the bandgap circuit due to its high predictability, and low dependence of the supply voltage and temperature of operation. This work studies a CMOS implementation of a resistor-less bandgap reference, which consumes low power. The most relevant and traditional approaches usually employed to implement bandgap voltage references are investigated. The impact of process, power-supply, load and temperature variations has been analyzed and simulated. The functionality of critical components of the circuit has been verified through chip implementation. / text

Dark current is an unwanted source of noise in images produced by digital imagers, the de facto standard of imaging. The two most common types of digital imager architectures, Charged-Coupled Devices (CCDs) and Complementary Metal-Oxide-Semiconductor (CMOS), are both prone to this noise source. To accurately reflect the information from light signals this noise must be removed. This practice is especially vital for scientific purposes such as in astronomical observations. Presented in this dissertation are characterizations of dark current sources that present complications to the traditional methods of correction. In particular, it is observed that pixels in both CCDs and CMOS image sensors produce dark current that is affected by the presence of pre-illuminating the sensor and that these same pixels produce a nonlinear dark current with respect to exposure time. These two characteristics are not conventionally accounted for as it is assumed that the dark current produced will be unaffected by charge accumulated from either illumination or the dark current itself. Additionally, a model reproducing these dark current characteristics is presented. The model incorporates a moving edge of the depletion region, where charge is accumulated, as well as fixed recombination-generation locations. Recombination-generation sites in the form of heavy metal impurities, or lattice defects, are commonly the source of dark current especially in the highest producing pixels, commonly called "hot pixels." The model predicts that pixels with recombination-generation sites near the edge of an empty depletion region will produce less dark current after accumulation of charge, accurately modeling the behavior observed from empirical sources. Finally, it is shown that activation energy calculations will produce inconsistent results for pixels with the presence of recombination-generation sites near the edge of a moving depletion region. Activation energies, an energy associated with the temperature dependence of dark current, are often calculated to characterize aspects of the dark current including types of impurities and sources of dark current. The model is shown to generate data, including changing activation energy values, that correspond with changing activation energy calculations in those pixels observed to be affected by pre-illumination and that produce inconsistent dark current over long exposure times. Rather than only being a complication to dark current correction, the presence of such pixels, and the model explaining their behavior, presents an opportunity to obtain information, such as the depth of these recombination-generation sites, which will aid in refining manufacturing processes for digital imagers.

Energetic particles from cosmic ray or terrestrial sources can strike sensitive areas of CMOS devices and cause soft errors. Understanding the effects of such interactions is crucial as the device technology advances, and chip reliability has become more important than ever. Particle accelerator testing has been the standard method to characterize the sensitivity of chips to single event upsets (SEUs). However, because of their costs and availability limitations, other techniques have been explored. Pulsed laser has been a successful tool for characterization of SEU behavior, but to this day, laser has not been recognized as a comparable method to beam testing. In this thesis, I propose a methodology of correlating laser soft error rate (SER) to particle beam gathered data. Additionally, results are presented showing a temperature dependence of SER and the "neighbor effect" phenomenon where due to the close proximity of devices a "weakening effect" in the ON state can be observed.