Wireless technology has revolutionized the way people communicate. From first generation, or 1G, in the 1980s to current, largely deployed 4G in the 2010s, we have witnessed not only a technological leap, but also the reformation of associated applications. It is expected that 5G will become commercially available in 2020. 5G is driven by ever-increasing demands for high mobile traffic, low transmission delay, and massive numbers of connected devices. Today, with the popularity of smart phones, intelligent appliances, autonomous cars, and tablets, communication demands are higher than ever, especially when it comes to low-cost and easy-access solutions. Existing communication architecture cannot fulfill 5G’s needs. For example, 5G requires connection speeds up to 1,000 times faster than current technology can provide. Also, from transmitter side to receiver side, 5G delays should be less than 1ms, while 4G targets a 5ms delay speed. To meet these requirements, 5G will apply several disruptive techniques. We focus on two of them: new radio and new scheme. As for the former, we study the non-orthogonal multiple access (NOMA) and as for the latter, we use mobile edge computing (MEC). Traditional communication systems allow users to communicate alternatively, which clearly avoids inter-user interference, but also caps the connection speed. NOMA, on the other hand, allows multiple users to transmit simultaneously. While NOMA will inevitably cause excessive interference, we prove such interference can be mitigated by an advanced receiver side technique. NOMA has existed on the research frontier since 2013. Since that time, both academics and industry professionals have extensively studied its performance. In this dissertation, our contribution is to incorporate NOMA with several potential schemes, such as relay, IoT, and cognitive radio networks. Furthermore, we reviewed various limitations on NOMA and proposed a more practical model. In the second part, MEC is considered. MEC is a transformation from the previous cloud computing system. In particular, MEC leverages powerful devices nearby and instead of sending information to distant cloud servers, the transmission occurs in closer range, which can effectively reduce communication delay. In this work, we have proposed a new evaluation metric for MEC which can more effectively leverage the trade-off between the amount of computation and the energy consumed thereby. A practical communication system for wearable devices is proposed in the last part, which combines all the techniques discussed above. The challenges for wearable communication are inherent in its diverse needs, as some devices may require low speed but high reliability (factory sensors), while others may need low delay (medical devices). We have addressed these challenges and validated our findings through simulations.

FPGA based systems have been heavily used to prototype and test Application Specic Integrated Circuit (ASIC) designs with much lower costs and development time compared to hardwired prototypes. In recentyears, thanks to both the latest technology nodes and a change in the architecture of reconfigurable integrated circuits (from traditional Complex Programmable Logic Device (CPLD) to full-CMOS FPGA), FPGAs have become more popular in embedded systems, both as main computation resources and as hardware accelerators. A new era is beginning for FPGA based systems: the partial run-time reconguration of a FPGA is a feature now available in products already on the market and hardware designers and software developers have to exploit this capability. Previous works show that, when designed properly, a system can improve both its power efficiency and its performance taking advantage of a partial run-time reconfigurable architecture. Unfortunately, taking advantage of run-time reconfigurable hardware is very challenging and there are several problems to face: the reconfiguration overhead is not negligible compared to nowadays CPUs performance,the reconfiguration time is not easily predictable, and the software has to be re-though to work with a time-evolving platform. This thesis project aims to investigate the performance of a modern run-time reconfigurable SoC (a Xilinx Zynq 7020), focusing on the reconfiguration overhead and its predictability, on the achievable speedup, and the trade-off and limits of this kind of platform. Since it is not always obvious when an application (especially a real-time one) is really able to use at its own advantage a partial run-time reconfigurable platform, the data collected during this project could be a valid help for hardware designers that use reconfigurable computing. / FPGA-baserade system har tidigare främst använts för snabb och kostnadseffektiv konstruktion av prototyper vid framtagandet av applikationsspecika integrerade kretsar (ASIC). På senare år har användandet av FPGA:er i inbyggda system för implementation av hårdvaruacceleratorers såväl som huvudsaklig beräkningsenhet ökat. Denna ökning har möjliggjorts mycket tack vare den utveckling som har skett av rekonfigurerbara integrerade kretsar: från de mer traditionella Complex Programmable Logic Devices (CPLD) till helt CMOS-baserade FPGA:er. Nu inleds en ny era för FPGA-baserade system tack vare möjligheten att under körning rekonfigurera delar av FPGA:n genom så kallad partial run-time reconguration(RTR) - en teknik som redan idag finns tillgänglig i produkter på marknaden. Tidigare forskning visar att användandet av en RTR-baserad hårdvaruarkitektur kan ha en positiv effekt med avseende på prestanda såväl som strömförbrukning. Att använda RTR-baserad hårdvara innebär dock flera utmaningar: En ej försumbar rekonfigurationstid måste tas i beaktning, så även den icke-deterministiska exekveringstiden som en rekonfiguration kan innebära. Vidare måste anpassningar av mjukvaran göras för att fungera med en hårdvaruplattform som förändras över tid. Denna uppsats syftar till att undersöka prestandan hos ett modernt RTRbaserat SoC (Xilinx Zynq 7020) med fokus på rekonfigurationstider och dess förutsägbarhet, prestanda ökning, begränsningar samt nödvändiga kompromisser som denna arkitektur innebär. Huruvida en applikation kan dra nytta av en RTR-baserad arkitektur eller inte kan vara svårt att avgöra. Den insamlade datan som presenteras i denna rapport kan dock fungera som stöd för hårdvarukonstruktörer som önskar använda en RTR-baserad plattform.