Graphene is an atomically thin two-dimensional (2-D) crystal with unique thermal, mechanical, and electronic transport properties such as the high mobility of carriers, perfect 2- D confinement and linear dispersion, etc., has been attracted many interest as a promising candidate for nano-scale devices over the past decades. Multilayer stacks of graphene and other stable, atomically thin, 2-D materials offer the prospect of creating a new class of heterostructure materials. Hexagonal boron- nitride (hBN), is a great candidate to be stacked with graphene due to an atomically 2-D layered structure with a lattice constant very similar to graphene (1.8% mismatch), large electrical band gap (∼4.7eV), and excellent thermal and chemical stability. The graphene/hBN based tunneling transistors show the resonant tunneling and strong negative differential resistance (NDR). These devices which have potential for future high-frequency and logic applications such as high-speed IC circuits, signal generators, data storage, etc., has been studied both theoretically and experimentally recently. The aim in this dissertation has been to study the effect of the uniaxial strain on the graphene nanoribbon resonant tunneling transistors (RTTs). The uniaxial strain may be induced either by an external stress applied to the graphene in a particular direction or by a substrate due to deposition of graphene on top of the other materials. The strain modifies distances between carbon atoms which leading to different hopping amplitudes among neighboring sites. A resonant tunneling transistor consisting of armchair graphene nanoribbon (AGNR) electrodes with three layers of hBN tunnel barrier between them has been considered. By using the nearest-neighbor tight-bind (TB) method and the nonequilibrium Green function (NEGF) formalism, the electronic transport characteristics of a RTT is calculated. In this work, we focus on how the strain affects the current-voltage characteristics of AGNR/hBN RTT.

abstract: This dissertation explores thermal effects and electrical characteristics in metal-oxide-semiconductor field effect transistor (MOSFET) devices and circuits using a multiscale dual-carrier approach. Simulating electron and hole transport with carrier-phonon interactions for thermal transport allows for the study of complementary logic circuits with device level accuracy in electrical characteristics and thermal effects. The electrical model is comprised of an ensemble Monte Carlo solution to the Boltzmann Transport Equation coupled with an iterative solution to two-dimensional (2D) Poisson’s equation. The thermal model solves the energy balance equations accounting for carrier-phonon and phonon-phonon interactions. Modeling of circuit behavior uses parametric iteration to ensure current and voltage continuity. This allows for modeling of device behavior, analyzing circuit performance, and understanding thermal effects. The coupled electro-thermal approach, initially developed for individual n-channel MOSFET (NMOS) devices, now allows multiple devices in tandem providing a platform for better comparison with heater-sensor experiments. The latest electro-thermal solver allows simulation of multiple NMOS and p-channel MOSFET (PMOS) devices, providing a platform for the study of complementary MOSFET (CMOS) circuit behavior. Modeling PMOS devices necessitates the inclusion of hole transport and hole-phonon interactions. The analysis of CMOS circuits uses the electro-thermal device simulation methodology alongside parametric iteration to ensure current continuity. Simulating a CMOS inverter and analyzing the extracted voltage transfer characteristics verifies the efficacy of this methodology. This work demonstrates the effectiveness of the dual-carrier electro-thermal solver in simulating thermal effects in CMOS circuits. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2019

abstract: ABSTRACT An Ensemble Monte Carlo (EMC) computer code has been developed to simulate, semi-classically, spin-dependent electron transport in quasi two-dimensional (2D) III-V semiconductors. The code accounts for both three-dimensional (3D) and quasi-2D transport, utilizing either 3D or 2D scattering mechanisms, as appropriate. Phonon, alloy, interface roughness, and impurity scattering mechanisms are included, accounting for the Pauli Exclusion Principle via a rejection algorithm. The 2D carrier states are calculated via a self-consistent 1D Schrödinger-3D-Poisson solution in which the charge distribution of the 2D carriers in the quantization direction is taken as the spatial distribution of the squared envelope functions within the Hartree approximation. The wavefunctions, subband energies, and 2D scattering rates are updated periodically by solving a series of 1D Schrödinger wave equations (SWE) over the real-space domain of the device at fixed time intervals. The electrostatic potential is updated by periodically solving the 3D Poisson equation. Spin-polarized transport is modeled via a spin density-matrix formalism that accounts for D'yakanov-Perel (DP) scattering. Also, the code allows for the easy inclusion of additional scattering mechanisms and structural modifications to devices. As an application of the simulator, the current voltage characteristics of an InGaAs/InAlAs HEMT are simulated, corresponding to nanoscale III-V HEMTs currently being fabricated by Intel Corporation. The comparative effects of various scattering parameters, material properties and structural attributes are investigated and compared with experiments where reasonable agreement is obtained. The spatial evolution of spin-polarized carriers in prototypical Spin Field Effect Transistor (SpinFET) devices is then simulated. Studies of the spin coherence times in quasi-2D structures is first investigated and compared to experimental results. It is found that the simulated spin coherence times for GaAs structures are in reasonable agreement with experiment. The SpinFET structure studied is a scaled-down version of the InGaAs/InAlAs HEMT discussed in this work, in which spin-polarized carriers are injected at the source, and the coherence length is studied as a function of gate voltage via the Rashba effect. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011