The programs that are easiest to write and understand are often not the most efficient. This thesis gives methods of converting programs of the former type to those of the latter type; this involves converting definitions of algorithms given as recursion equations using high level primitives into lower level flow chart programs. The main activities involved are recursion removal (c.f. Strong), loop elimination, and the overwriting of shared structures. We have concentrated on the semantics, rather than the syntax, of the programs we are transforming and we have used techniques developed in work done on proving the correctness of programs. The transformations are done in a hierarchical manner and can be regarded as compiling a program defined in a structured manner (Dijkstra) to produce an efficient low level program that simulates it. We describe the implementation of a system that allows the user to specify algorithms in a simple set language and converts them to flow chart programs in either a bitstring or list processing language. Both of these lower languages allow the sharing of structures. The principles are applicable to other domains and we describe how our system can be applied more generally.

This dissertation examines fundamental issues that face the designers of any distributed programming language. It considers how programs are structured, how processes communicate and synchronize, and how hardware failures are represented and handled. We discuss each of these issues and argue for a particular approach based on our application domain: distributed systems (such as distributed operating systems) and distributed user applications. We conclude that a language for such applications should include the following mechanisms: dynamic modules, shared variables (within a module), dynamic processes, synchronous and asynchronous forms of message passing, rendezvous, concurrent invocation, and early reply. We then describe the current SR language, which has evolved considerably based on our experience. SR provides the above mechanisms in a way that is expressive yet simple. SR resolves the tension between expressiveness and simplicity by providing a variety of mechanisms based on only a few underlying concepts. The main language constructs are still resources and operations. Resources encapsulate processes and the variables they share; operations provide the primary mechanism for process interaction. One way in which SR has changed is that both resources and processes are now created dynamically. Another change is that all the common mechanisms for process interaction--local and remote procedure call, rendezvous, dynamic process creation, asynchronous message passing, and semaphores--are now supported by a novel integration of the mechanisms for invoking and servicing operations. Many small and several larger examples illustrate SR's mechanisms and the interplay between them; these examples also demonstrate the language's expressiveness and flexibility. We then describe our implementation of SR. The compiler, linker, and run-time support are summarized. We then focus on how the generated code and run-time support interact to provide dynamic resources and to generate and service invocations. We also describe optimizations for certain operations. Measurements of the implementation's size and cost are given. The implementation has been in use since November 1985 and is currently being improved. Finally, we justify SR's syntax and semantics and examine how its mechanisms compare to other approaches to distributed programming. We also discuss how SR balances expressiveness, simplicity, and efficiency.

DESIRE P is a general purpose continuous time simulation language suitable for interactive simulation, dynamic system study, mathematical modeling, process control analysis. It includes an interactive editor, file manipulation facilities, and graphic packages, making it a completely self-contained system. The PDP-11 version of DESIRE P handles 20 state variables, while the VAX/VMS version runs 150 or more. An interpreted job-control language serves for interactive program entry, editing and file operations, and for programming multirun simulation studies. The dynamic segment, containing differential equations in first-order form, is entered just like the job-control statments and accesses the same variables. DESIRE P is largely written in PASCAL, and most of it can be transferred to different computers, with little change. The PASCAL implementation proves that the high-level language can be used to program direct executing languages, still keeping efficiency and speed comparable to assembly language. The runtime compiler of DESIRE P generates fast and efficient code. DESIRE P can incorporate existing and new precompiled FORTRAN numerical integration algorithms.

No description available.

The majority of applications running over packet networks involve point-to-point working. Over the last few years, there has been growing interest in applications involving multiple participants and, increasingly, where these participants are all simultaneously involved in the communication. This interest has strengthened with the introduction of the MBone (the Internet multicasting backbone) and with the range of services made possible by ATM and those envisaged for Broadband ISDN. This thesis discusses the potential for a wide variety of multi-party applications. It examines their detailed requirements and the support mechanisms needed to meet these requirements. The work is presented as a dissertation and a collection of work published over a period of about ten years and as such draws together work on multi-party communication undertaken by the author and postgraduate students under her supervision. The major contribution of the thesis and the most recent work concerns multicast routing strategies capable of supporting high-bandwidth delay sensitive applications. A new heuristic is introduced which is shown to offer efficient routing solutions whilst ensuring that delays to each participant are kept within a bound. The heuristic is reasonably simple and is shown to perform well under a variety of conditions. The chapters of the these leading up to the work on multicast routing present the earlier published work. Architectural frameworks are presented which extend existing protocol reference models to offer multicast support mechanisms at appropriate hierarchical levels with a view to flexible yet efficient use of the network. One important support mechanism is group management and a system developed in the context of an integrated services network is described. This comprises a group management database together with a collection of flexible group management procedures capable of supporting a wide variety of applications.

The environment of space is challenging to digital equipment due to the interaction between electrical systems and the radiation of space. One such effect is the Single Event Upset (SEU), which occurs when radiation causes a logical bit value to change. These effects are magnified in reconfigurable digital systems that utilize Field Programmable Gate Arrays (FPGA) because both the configuration and the data are susceptible to SEUs. Several techniques have been developed in order to mitigate these effects. One such technique, called Triple Modular Redundancy (TMR), is an architecture where three identical systems perform the same operation in parallel. The three outputs are applied to a voter circuit which would eliminate an SEU caused error. This thesis develops a five-stage pipelined Reduced Instruction Set Computer (RISC) microprocessor. A TMR architecture is then instantiated on an FPGA based circuit board. Instead of voting the processor outputs, the voting function is distributed and votes the outputs of all the internal pipeline registers. Even in the event of an SEU caused error, correct data is applied to the next pipeline stage. Finally this thesis describes and analyzes test data from radiation testing of the TMR system.

Field Programmable Gate Arrays (FPGAs) provide a reconfigurable asset in the design of space computing. â Hardwareâ configurations are stored in FPGA memory elements, which are susceptible to Single Event Upsets (SEUs). What is the best way to detect and mitigate SEUs and correct them before they become functional errors? The Configurable Fault Tolerant Processor (CFTP) consists of a controller FPGA (X1) controlling an experiment FPGA (X2), which can be used to test different fault-mitigation techniques. This focus of this thesis was to develop and execute a radiation test plan to evaluate different experiments in a proton radiation beam at Crocker Nuclear Laboratory, Davis, CA. A shift register was designed to determine a proton flux conducive to SEU observation. The shift register was also modified to create two additional configurations, implemented with the memory elements of the Look-Up Table and Flip-flops within an FPGA Configurable Logic Block. The data collected from this program was then analyzed for SEU rates and fault susceptibility. This data was extrapolated using a radiation environment model to predict the on-orbit SEU-rate for CFTP in the NPSAT1 orbit of 560 km, 35.4 degrees inclination, as well as Virtex II FPGAs and at 1000 and 1500 km altitudes.

The wirelessly networked opportunistic digital array radar (WNODAR) system combines opportunistic phased array and aperstructure concepts. The array elements contain standâ alone transmitâ receive (T/R) modules with no hardwire connections other than prime power and are wirelessly networked to a central controller and processor unit. A fullâ scale WNODAR operating in the VHF/UHF frequency bands (300 MHz) exhibits many favorable properties, which make the system suitable for ballistic missile defense (BMD) early warning radar (EWR) applications. In order to validate the WNODAR concepts, demonstration arrays consisting of T/R modules realized using field programmable gate array (FPGA) technology are developed. The demonstration units are frequency scaled from the projected VHF/UHF frequency range to S-band (2.4 GHz) to make use of the abundance of commercial off the shelf (COTS) wireless communication components. This research primarily relates to the development of a demonstration T/R module and the evaluation and characterization of component devices. Design, analysis and simulation of an eightâ element demonstration array using MATLAB and CST Microwave Studio were conducted to examine expected array beam patterns.

Many problems in programming involve pairs of computations that cancel out each other's effects; some examples include parsing/printing, embed- ding/ projection, marshalling/unmarshalling, compressing/ de-com pressing etc. To avoid duplication of effort, the paradigm of bidirectional programming aims at to allow the programmer to write a single program that expresses both computations. Despite being a promising idea, existing studies mainly focus on the view-update problem in databases and its variants; and the impact of bidirectional programming has not reached the wider community. The goal of this thesis is to demonstrate, through concrete language designs and case studies, the relevance of bidirectional programming, in areas of computer science that have not been previously explored. In this thesis, we will argue for the importance of bidirectional programming in programming language design and compiler implementation. As evidence for this, we will propose a technique for incremental refactoring, which relies for its correctness on a bidirectional language and its properties, and devise a framework for implementing program transformations, with bidirectional properties that allow program analyses to be carried out in the transformed program, and have the results reported in the source program. Our applications of bidirectional programming to new areas bring up fresh challenges. This thesis also reflects on the challenges, and studies their impact to the design of bidirectional systems. We will review various design goals, including expressiveness, robustness, updatability, efficiency and easy of use, and show how certain choices, especially regarding updatability, can have significant influence on the effectiveness of bidirectional systems.

A dissertation submitted to the Faculty of Science, University of the Witwatersrand, in fulfilment of the requirements for the degree of Master of Science Johannesburg 2016. / This dissertation investigates grit “passion and perseverance” for a long-term goal and growth mindset in grade 11 high school students as they code a non-trivial pro-gramming project in Java over a six-week period. Students are often challenged by the complexities of programming and can be overwhelmed when they encounter errors causing them to give up and not persevere. The programming project includes scaffolding with frequent feedback to increase the motivation of students. The study used mixed methods research that used both quantitative and qualitative data to find answers to the research questions. Whilst the correlation between grit, mindset and the project results were moderate, that students submitted their project numerous times showed an indication to perseverance. The data gathered from the interviews further indicated that the students’ perseverance led them to employ their own prob-lem-solving strategies when they encounter problems. / MT 2017