High resolution imaging devices have made a digital medical archiving system feasible. The large volumes of information generated must be stored and retrieved at high data rates in order to insure the timely diagnosis of patients. This creates some unique technological challenges that must be resolved, including the problem dealing with multiple vendor products interacting in one environment. The high speed interface card design presented in this thesis is able to deal with different computer host busses as well as different interprocessor communication protocols. The ACR-NEMA standard has been implemented in the design as one possible network protocol that provides a solution that can be easily adapted to different vendors. The design has been analyzed using the Network II.5 simulation language. The simulation was performed to insure that the original objectives are met and to determine the impact on the protocols rated throughput.

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Thesis (Masters Diploma (Technology)-- Cape Technikon, Cape Town,1988 / Brown Davis and McCorquodale is one of the major suppliers of cheques to the banking industry. To produce these cheques they use a number of different print systems, one of which comprises of a minicomputer, an industry standard tape deck and two printers, a Diablo daisywheel and a Control Data Corporation (CDC) printer which was extensively modified to cater for the requirements of the cheque printing industry. The CDC printer is used to print the code line on the cheques using magnetic ink. After each line is printed the computer sends a form feed command which causes the printer to throw paper. This throw is controlled by a paper tape, known as a Vertical Format Unit tape, or rather a VFU tape. This tape has holes punched into it at specific places which determine the amount of paper throw also known as vertical feed. The holes are sensed by brushes which are pulled up to 5 volt when they pass over a hole and touch a roller connected to the 5 volt line. This system, being of an electro-mechanical nature, is prone to faults and causes much down time due to mechanical wear on the brushes and dirt on the roller. This means that the brushes have to be adjusted and therefore also means that the timing has to be readjusted each time. The timing relationships are discussed in Section 2.B

Thesis (M.Diploma in Technology)--Cape Technikon, Cape Town, 1993 / This thesis describes the design, development and implementation of an intelligent printer sharer, capable of servicing ten personal computers and two printers.

This paper describes the building of a parallel converter for a high-speed serial bus. The high-speed serial port of the Macintosh personal computer is used to implement the bus, while an MC68000 Educational Computer Board is used to perform the serial-to-parallel conversion. The device's performance is evaluated, and possible methods for improving its performance are discussed.

This paper describes the design and simulation of a network interface unit (NIU) for a picture archiving and communication system (PACS) network called PACnet. PACnet is a dual fiber optic ring network under development at the Computer Engineering Research Laboratory of the University of Arizona. This network integrates voice, data, and image communications in a hospital environment and supports a throughput rate between 200-500 megabits per second. At each node in the network, an NIU implements the Data Link Layer and Physical Layer protocols of PACnet. The initial network interface unit design for PACnet was a functional description of NIU protocols and major components. In order to construct a demonstration prototype of PACnet,the NIU description must be refined and an architecture must be specified. The NIU design is specified and simulated using the hardware description language VHDL. Simulation results provide information on NIU timing characteristics and logic families required to implement the NIU.

Hardware/Software (HW/SW) interfaces are pervasive in computer systems. However, many HW/SW interface implementations are unreliable due to their intrinsically complicated nature. In industrial settings, there are three major challenges to improving reliability. First, as there is no systematic framework for HW/SW interface specifications, interface protocols cannot be precisely conveyed to engineers. Second, as there is no unifying formal model for representing the implementation semantics of HW/SW interfaces accurately, some critical properties cannot be formally verified on HW/SW interface implementations. Finally, few automatic tools exist to help engineers in HW/SW interface development. In this dissertation, we present an automata-theoretic approach to HW/SW co-verification that addresses these challenges. We designed a co-specification framework to formally specify HW/SW interface protocols; we synthesized a hybrid Büchi Automaton Pushdown System, namely Büchi Pushdown System (BPDS), as the unifying formal model for HW/SW interfaces; and we created a co-verification tool, CoVer that implements our model checking algorithms and realizes our reduction algorithms for BPDS. The application of our approach to the Windows device/driver framework has resulted in the detection of fifteen specification issues. Furthermore, utilizing CoVer, we discovered twelve real bugs in five drivers. These non-trivial findings have demonstrated the significance of our approach in industrial applications.

Parallelism can use existing technology in computer communications network design to provide higher data rates and a greater degree of flexibility than monolithic systems. This research investigates the design of a high-speed Parallel Local Area Network (PLAN) interface. It defines the goals of a PLAN interface as low data latency, high data throughput, scalability, and low cost. Three fundamental PLAN interface categories are proposed to meet these goals. These categories are single-bus, dual-bus, and bus-free adaptors. The relative merits of each category are discussed in terms of suitability to several adaptor applications. Each category is further explored by developing a VHDL model of a representative system. The latency, throughput, and component utilization of each model is measured. For medium to large data sets, the dual-bus design provides slightly greater throughput when transmitting encoded data. When transmitting medium to large unencoded data sets, the bus-free design yields marginally higher throughput. In nearly all cases the bus-free design has a greater latency than either of the bus-based design options. Other insights gained from the models regarding physical construction of each adaptor type are also presented. / Master of Science