Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 1990. / Thesis Advisor(s):Butler, Jon T. "June 1990." Description based on title screen as viewed on October 15, 2009. DTIC Identifier(s): Computer Logic. Author(s) subject terms: Multi-Valued Logic, Minimization, PLA, Back-tracking. Includes bibliographical references (p. 36-37). Also available in print.

No description available.

No description available.

The first part of the thesis provides an introduction to the logic programming language Prolog and some areas of current research. The use of compilation to make Prolog faster and more efficient is studied and a modified representation for complex structures is presented. Two programming tools are also presented. The second part of the thesis focuses on one problem which arises when implementing an Expert System using Prolog. A practical three-valued Prolog implementation is described. An interpreter accepts three-valued formulae and converts these into a Prolog representation. Formulae are in clausal form which allows disjunctive conclusions to rules. True and false formulae are stated explicitly and therefore the interpreter is able to perform useful consistency checks when information is added to the data base.

No description available.

The wakeup logic in out-of-order superscalar microprocessors is responsible for resolving the data dependency hazard between instructions. Its performance is critical because it may prevent the processor to have deeper pipelines or to achieve the highest IPC (Instructions Per Cycle) possible. In this thesis, we implemented the circuit and layout for two types of wakeup logic (CAM-type and RAM-type) used in the modem microprocessors. These two implementations are simulated extensively using a circuit level simulator - HSPICE, with full parasitic loads. We, then, made comparison between the CAM-type and RAM-type wakeup circuits. From the simulation results, the CAM-type wakeup logic has a better performance than the RAM-type wakeup logic if a larger number of physical registers is employed by the processor. The performance impacts caused by varying the other superscalar design parameters, such as instruction window size and issue width, are not much different for both types of wakeup logic implementations. / Graduation date: 2003

This thesis presents an approach to image classification via a Multi-Layer Perceptron (MLP) Artificial Neural Network (ANN) on the SRC-6 reconfigurable computer for use in classifying Low Probability of Intercept (LPI) radar emitters. The rationale behind the previously unexplored use of new reconfigurable computers combined with neural networks for this application is the potential for near real-time classification. Current potential near-peer competitors have access to LPI technology, so development of quick classification methods is crucial for ships to determine intent and to enable the possibility for self-defense against these types of emitters. The neural network, based on work conducted by Professor Phillip E. Pace of the Naval Postgraduate School (NPS), generates integer-cast weights by first using a sequential processor to conduct floating-point backpropagation to train the network on potential timefrequency images that allows generation of weights with lower overall Root Mean Squared (RMS) errors. The weights are then used in a parallel-processing reconfigurable computer for close to real-time classification. A second method of direct pixel comparison using Exclusive-Or (XOR) logic is presented as an alternative image classification method. Comparisons to similar representations in C++ are provided, for use in judging comparative error levels and timing between parallel and sequential processing methods.

Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 141-155). Available also in a digital version from Dissertation Abstracts.

Thesis (Ph.D.)--Australian National University, 2005.

M.Sc. (Mathematics) / This dissertation describes the solution toa specific logical problem, the satisfiability problem, in a logic of games called Alternating-time Temporal Logic (ATL). Computation Tree Logic (CTL) is a discrete branching-time temporal logic for reasoning about labelled transition systems. ATL extends CTL to describe gametheoretic situations, where multiple agents together determine the evolution of the system. In particular, ATL explicitly provides for describing the abilities of coalitions of agents in such systems. Weprovide an automata-based decision procedure for ATL by translating the satisfiability problem for an ATL formula to the nonemptiness problem for an Alternating Biichi 'free Automaton. The key result that enables this translation is a oundedbranching tree model theorem for ATL, proving that a satisfiable formula is also satisfiable in a tree model of bounded branching degree. In terms of complexity, we show that satisfiability in ATL is complete for exponential time, which agrees with the corresponding complexity result for the fragment CTL. Closely related to ATL is an independently developed family of modal logics, the Coalition Logics. The presented results also provide a satisfiability procedure for Extended Coalition Logic interpreted over strongly playable coalition models. The structure of the dissertation is as follows: • Chapter 1 is an introduction to the topic, provides an overview of the results and a preview of the dissertation. • Chapter 2 presents some mathematical preliminaries regarding trees, automata, fixed points and game theory. • Chapter 3 discusses CTL and in particular an automata-based satisfiability procedure for CTL. • Chapter 4 introduces Alternating-time Temporal Logic (ATL) as a logic of games. • Chapter 5 contains the main results of the dissertation: first we prove a boundedbranching tree model property for ATL. Then the construction of the required automaton for satisfiability checking is described. • Chapter 6 relates the present work to some other logics of games, and in particular the Coalition Logics. • Chapter 7 finalises the dissertation with a conclusion and a look at some future research directions that might be pursued following the present work.