Thesis (Ph. D.)--University of Texas at Austin, 2005. / Supervisor: Simon S. Lam. Vita. Includes bibliographical references.

Thesis (M.S.)--Brigham Young University. Dept. of Computer Science, 2006. / Includes bibliographical references (p. 45-48).

Reliable routing using alternate paths is investigated in this dissertation. We propose precalculated alternate paths as a method for fast recovery from link and node failures in IP networks. We demonstrate that path switching time, and thus failure recovery time are, as expected, considerably faster than the standard method of recalculating a new path on the fly. However, to be effective, the alternate paths should share a minimal set of links and nodes - preferably none - with the failed path. As shared links are considered in this work, we give a reliability model for this situation (non-disjoint alternate paths) and develop estimates of reliability as a function of the number of shared links. Alternate path finding algorithms to calculate suitable alternate paths subject to predefined constraints are also developed. Implementation of these techniques for improving routing reliability is shown to be straightforward for explicit routing protocols such as Multi-Protocol Label Switching (MPLS) with Explicit Routing mode. This mode is expected to be the protocol of choice for applications requiring guaranteed Quality of Service (QoS) carried on the coming generation of wavelength-switched networks (Internet II, CA Net III, etc.) We propose a Reliable MPLS (R-MPLS) protocol by applying alternate path routing to MPLS, using our new algorithms to precalculate appropriate alternate paths. Simulation results show that R-MPLS can achieve fast recovery from failures. We also address reliability issues for the problem of optimal Service Level Agreement (SLA) admission control. To achieve reliable admission control, we apply alternate path routing to an existing SLA-based admission controller called SLAOpt. In the existing Utility Model, SLA admission control is mapped to the Multiple-Choice Multi-Dimension Knapsack Problem (MMKP), where the aim is to maximize system utility (i.e., revenue). However, SLAOpt is static in terms of network topology and does not consider reliability. Motivated by this, we propose a Reliable SLAOpt (R-SLAOpt), in which utility optimization is subject to the additional constraint of reliability. A new algorithm was also developed to calculate multiple groups of alternate paths that meet the desired QoS demands and reliability requirement. After QoS adaptation, R-SLAOpt selects an appropriate path group containing two or three paths for each admitted session and performs resource reservation on all paths in the group. In the event of node or link failure, a session can be quickly switched to one of the alternate paths, maintaining the guaranteed QoS without having to run the full admission algorithm again. In this way, we have obtained a unified treatment of routing reliability and optimal SLA admission control. Finally, simulations are presented which investigate R-SLAOpt's impact on system performance and the gains made in reliability. / Graduate

Reachability analysis is one of the earliest and most common techniques for protocol validation. It is well suited to checking the protocol syntactic properties since they are a direct consequence of the structure of the reachability tree. However, validations of unbounded protocols via reachability analysis always lead to the "state explosion" problem. To overcome this, a new approach in reachability analysis has been proposed by Vuong et al [Vuong 82a, 83a]. While not loosing any information on protocol syntactic properties, the Teachability tree constructed by the new approach for all non-FIFO and for a particular set of FIFO protocols (called well-ordered protocols) will become finite. This thesis is concerned with the implementation of an integrated package called VALIRA (VALIdation via Reachability Analysis) which bases on both the proposed technique and the conventional technique. Details and implementation of the various approaches used in VALIRA are presented in order to provide an insight to the package. Various features of the package are demonstrated with examples on different types of protocols, such as the FIFO, the non-FIFO, and the priority protocols. The use of VALIRA was found to be practical in general, despite some limitations of the package. Further enhancements on the VALIRA are also suggested. / Science, Faculty of / Computer Science, Department of / Graduate

With the increasing need for distributed processing and computer networking, the demand for open systems interconnection (OSI) has also increased. In [Davis-88], Davis et al propose a new generation portable protocol tester that will be able to provide conformance testing for OSI protocol implementations. In this thesis report, a specialized programmable hardware module, called protocol decoding accelerator (PDA), is designed to be used as the PDU decoder engine being defined in the Davis architecture. PDU decoding is the process of parsing the PDU header fields into a data structure that can be more readily used by other processes. Decoding can be time consuming because there is a large variety of PDU fields and formats. Conventional approach to PDU decoding is often implemented as software program designed for general purpose processor architecture. However, most general purpose processors do not handle PDU decoding efficiently. There are other VLSI protocol controllers, but they all have limited programmability and flexibility. The PDA is developed based on a simple instruction set with dedicated hardware to optimize important functions. Using selected PDU types and decoding programs from OSI layer 2 to 4 protocols, the resulting PDA design shows a minimum of 16 times faster average execution time and about five times smaller program size when compared to a 68000 system. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

No description available.

No description available.

published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

This dissertation is concerned with the design of a generic gateway which provides an interoperability between dissimilar computer networks. The generic gateway is decomposed with subnetwork dependent blocks and subnetwork independent blocks. The subnetwork dependent block is responsible to communicate with subnetwork nodes. The subnetwork independent block is responsible to interconnect the subnetwork dependent blocks. The communications between subnetwork dependent and independent blocks are done by service access points which defined independently to any specific subnetworks. Formal specification of a generic gateway is provided by LOTOS. The generic gateway specification is tested by a verifiable test method which is proposed in this dissertation. The correctness of the specification has been verified while the specified model is simulated. The major difference between conventional simulation and the verifiable test is in the objective of simulation. In the verifiable test method, the semantical properties are examined during the simulation process. The tester can be either human observer or other process.

by Wong, Chan-foon. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1993. / Includes bibliographical references (leaves 59-67 (1st gp.)). / Chapter Chapter I --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.2 --- Traffic Characteristics --- p.2 / Chapter 1.3 --- Related Works --- p.5 / Chapter Chapter II --- Integrated Services Protocol (ISP) --- p.7 / Chapter 2.1 --- Ethernet --- p.7 / Chapter 2.2 --- ISP Description --- p.9 / Chapter 2.2.1 --- Voice Communications Characteristics --- p.9 / Chapter 2.2.2 --- Voice Packet Format --- p.12 / Chapter 2.2.3 --- Call Management --- p.13 / Chapter 2.4.4 --- Voice Packet Transmission Protocol --- p.14 / Chapter 2.4.5 --- Error Handling --- p.16 / Chapter Chapter III --- Protocol Studies --- p.17 / Chapter 3.1 --- Simulation Model And Parameters --- p.17 / Chapter 3.2 --- Voice Loss --- p.18 / Chapter 3.3 --- Data Delay --- p.20 / Chapter 3.4 --- Maximum Number Of Active Voice Stations --- p.22 / Chapter 3.5 --- Summary --- p.23 / Chapter Chapter IV --- Implementation --- p.24 / Chapter 4.1 --- System Platform --- p.24 / Chapter 4.2 --- Integrated Services Adapter (ISA) --- p.25 / Chapter 4.2.1 --- Hardware Design --- p.26 / Chapter 4.3 --- Voice on Ethernet Adapter (VEA) --- p.29 / Chapter 4.3.1 --- Hardware Design --- p.29 / Chapter 4.3.2 --- Software Design --- p.31 / Chapter 4.3.2.1 --- Programming The VEA --- p.32 / Chapter 4.3.2.2 --- Software Development Under DOS --- p.35 / Chapter 4.3.2.3 --- Software Development Under Linux --- p.37 / Chapter 4.4 --- Summary --- p.41 / Chapter Chapter V --- Implementation Results --- p.42 / Chapter 5.1 --- Frequency Response --- p.43 / Chapter 5.2 --- Distortion --- p.44 / Chapter 5.3 --- Amplification and Linearity --- p.45 / Chapter 5.4 --- Voice Quality With Different Voice Packet Sizes --- p.46 / Chapter 5.5 --- Voice Loss Under Various Data Loadings --- p.47 / Chapter Chapter VI --- Implementation Experiences --- p.49 / Chapter 6.1 --- CPU Bottle-neck --- p.49 / Chapter 6.2 --- Data Bus Bottle-neck --- p.50 / Chapter 6.3 --- Operating System --- p.50 / Chapter Chapter VII --- Future Works --- p.52 / Chapter 7.1 --- Enhancement of ISA --- p.52 / Chapter 7.2 --- Extensions To Other Networks --- p.53 / Chapter 7.3 --- A New Architecture For Future Multimedia Workstation --- p.54 / Chapter Chapter VIII --- Conclusions --- p.57 / Bibliography --- p.59 / Appendices --- p.A.l / Appendix A: Detailed Circuit Designs --- p.A.2 / Appendix B: Detailed Software Designs --- p.A.5 / Appendix C: Schematic Diagrams --- p.A.15 / Appendix D: Program Listings --- p.A.23