Thesis (Ph. D.)--University of Hawaii at Manoa, 2003. / Includes bibliographical references (leaves 108-113).

Thesis (Ph. D.)--Oregon State University, 2008. / Printout. Includes bibliographical references (leaves 103-109). Also available on the World Wide Web.

M.Ing.

Thesis (M. Eng.)--Carleton University, 2002. / Includes bibliographical references (p. 88-92). Also available in electronic format on the Internet.

Thesis (Ph. D.)--University of Hawaii at Manoa, 2001. / Includes bibliographical references (leaves 145-150). Also available on microfiche.

With the increasing need for distributed processing and computer networking, the demand for open systems interconnection (OSI) has also increased. In [Davis-88], Davis et al propose a new generation portable protocol tester that will be able to provide conformance testing for OSI protocol implementations. In this thesis report, a specialized programmable hardware module, called protocol decoding accelerator (PDA), is designed to be used as the PDU decoder engine being defined in the Davis architecture. PDU decoding is the process of parsing the PDU header fields into a data structure that can be more readily used by other processes. Decoding can be time consuming because there is a large variety of PDU fields and formats. Conventional approach to PDU decoding is often implemented as software program designed for general purpose processor architecture. However, most general purpose processors do not handle PDU decoding efficiently. There are other VLSI protocol controllers, but they all have limited programmability and flexibility. The PDA is developed based on a simple instruction set with dedicated hardware to optimize important functions. Using selected PDU types and decoding programs from OSI layer 2 to 4 protocols, the resulting PDA design shows a minimum of 16 times faster average execution time and about five times smaller program size when compared to a 68000 system. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2004. Directed by Russell M. Mercereau. / Vita. Includes bibliographical references (leaves 90-92).

No description available.

This thesis addresses the problem of decoding high rate convolutional codes directly without resorting to puncturing. High rate codes are necessary for applications which require high bandwidth efficiency, like high data rate communication systems and magnet recording systems. Convolutional ( rate k/n) codes, used as component codes for turbo codes, are preferred for their regular trellis structure and the resulting ease in decoding. However, the branch complexity of the (primal) code trellis increases exponentially with 'k' for k/(k+1) codes, making decoding on the code trellis quickly impractical with increasing code rate. 'Puncturing' is the method traditionally used for generating high rate codes, which keeps the decoding complexity nearly the same for a wide range of code rates, since the same 'mother' code decoder is used at the receiver, while only the puncturing and depuncturing pattern is altered for changes in code rate. However, 'puncturing' puts a constraint in the search for the best possible high rate code, thereby resulting in a performance penalty, particularly at high SNRs. / Thesis (PhD)--University of South Australia, 2008.

Thesis (M.S.)--Ohio University, November, 2003. / Title from PDF t.p. Includes bibliographical references (leaves 68-70).