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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Iterative multistage maximum likelihood decoding algorithm for multilevel codes and its applications

Stojanović, Diana. January 2003 (has links)
Thesis (Ph. D.)--University of Hawaii at Manoa, 2003. / Includes bibliographical references (leaves 108-113).
2

Low-complexity high-speed VLSI design of low-density parity-check decoders /

Cui, Zhiqiang. January 1900 (has links)
Thesis (Ph. D.)--Oregon State University, 2008. / Printout. Includes bibliographical references (leaves 103-109). Also available on the World Wide Web.
3

Insertion/deletion detection and bit-resynchronisation using the viterbi algorithm

Santos, Marco Paulo Ferreira dos 26 February 2009 (has links)
M.Ing.
4

Implementation of iterative decoding algorithms on digital VLSI platforms /

Zarkeshvari, Farhad, January 1900 (has links)
Thesis (M. Eng.)--Carleton University, 2002. / Includes bibliographical references (p. 88-92). Also available in electronic format on the Internet.
5

Binary mapping of nonbinary codes and soft decision decoding algorithms of Reed-Solomon codes based on bit reliability

Hu, Ta-Hsiang. January 2001 (has links)
Thesis (Ph. D.)--University of Hawaii at Manoa, 2001. / Includes bibliographical references (leaves 145-150). Also available on microfiche.
6

A Protocol decoding accelerator (PDA)

Wan, Ching Leong January 1990 (has links)
With the increasing need for distributed processing and computer networking, the demand for open systems interconnection (OSI) has also increased. In [Davis-88], Davis et al propose a new generation portable protocol tester that will be able to provide conformance testing for OSI protocol implementations. In this thesis report, a specialized programmable hardware module, called protocol decoding accelerator (PDA), is designed to be used as the PDU decoder engine being defined in the Davis architecture. PDU decoding is the process of parsing the PDU header fields into a data structure that can be more readily used by other processes. Decoding can be time consuming because there is a large variety of PDU fields and formats. Conventional approach to PDU decoding is often implemented as software program designed for general purpose processor architecture. However, most general purpose processors do not handle PDU decoding efficiently. There are other VLSI protocol controllers, but they all have limited programmability and flexibility. The PDA is developed based on a simple instruction set with dedicated hardware to optimize important functions. Using selected PDU types and decoding programs from OSI layer 2 to 4 protocols, the resulting PDA design shows a minimum of 16 times faster average execution time and about five times smaller program size when compared to a 68000 system. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate
7

Error resilient video coding for wireless applications

Jung, Kyunghun, January 2003 (has links) (PDF)
Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2004. Directed by Russell M. Mercereau. / Vita. Includes bibliographical references (leaves 90-92).
8

Computer simulation of Viterbi decoders

Honda, Makoto, 1950- January 1976 (has links)
No description available.
9

Dual domain decoding of high rate convolutional codes for iterative decoders /

Srinivasan, Sudharshan. Unknown Date (has links)
This thesis addresses the problem of decoding high rate convolutional codes directly without resorting to puncturing. High rate codes are necessary for applications which require high bandwidth efficiency, like high data rate communication systems and magnet recording systems. Convolutional ( rate k/n) codes, used as component codes for turbo codes, are preferred for their regular trellis structure and the resulting ease in decoding. However, the branch complexity of the (primal) code trellis increases exponentially with 'k' for k/(k+1) codes, making decoding on the code trellis quickly impractical with increasing code rate. 'Puncturing' is the method traditionally used for generating high rate codes, which keeps the decoding complexity nearly the same for a wide range of code rates, since the same 'mother' code decoder is used at the receiver, while only the puncturing and depuncturing pattern is altered for changes in code rate. However, 'puncturing' puts a constraint in the search for the best possible high rate code, thereby resulting in a performance penalty, particularly at high SNRs. / Thesis (PhD)--University of South Australia, 2008.
10

Modified Viterbi decoding algorithms for high dimensional trellis coded modulation

Huang, Zhiyong. January 2003 (has links)
Thesis (M.S.)--Ohio University, November, 2003. / Title from PDF t.p. Includes bibliographical references (leaves 68-70).

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