實體造型在各種設計和生產項目中起著關鍵的作用。他們作為虛擬雕刻，微結構設計和快速成型等等這些常常需要處理複雜形狀和拓撲模型的應用的基礎。隨著愈來愈複雜性的工業模型和需要執行重複性的操作，我們必須要有一個有效率的處理系統。然而，因為許多基本的幾何運算是計算密集型的，一般商用的幾何內核（例如Parasolid和ACIS），尤其是對自由曲面和高度詳細複雜的模型，計算成本的要求是非常高，甚至有時不能使用。本研究的目的是開發一個以自由曲面模型為對象能夠完全在GPU 上運行的實體建模，這將大大提高建模的效率。 / 引致操作中高計算強度的一個關鍵原因是因為他們使用了邊界表示法（B-REP）。我們引入了一個新的表述 - 名為多層深度法向圖像（LDNI）來直接在GPU 上描述對象。LDNI 能夠滿足一定的幾何和拓撲的要求，同時保持簡單和易於並行實現，提供了一個比邊界表示法更可行的形式。 / 在基於B-REP 的建模核心內執行基本操作（如布爾運算，閔可夫斯基和等）往往是耗時和容易出現偶爾失敗。我們已經開發出一些GPU 加速算法，包括布爾和一般閔可夫斯基和，它們的執行速度遠遠超過傳統的方法並且沒有顯著的穩定性問題出現。這些算法是基於圖像表示法來進行的，可以讓特定的任務在每個像素上獨立運行。 / 我們還開發了在GPU 上由B-REP 轉換成LDNI 和由LDNI 轉換成B-REP 的算法。我們為了高效率而使用光栅化來獲得圖像並利用GPGPU 庫來將圖像轉換成B-REP。有了這些算法，我們的建模框架可以與其他常見的CAD 內核進行交換操作。這框架還支持模型的局部細化網格，這有助減少內存消耗，並同時保持曲面G¹ 連續性。 / 最後，本研究的目的是提供一個全面處理複雜形狀的建模問題的框架。我們展示幾個使用了以GPU 為基礎的實體建模應用例子，相比現有的以B-REP 為基礎的系統，我們的框架在效率上得到極大的改善。 / Solid modeling plays a key role in a variety of design and manufacturing activities. They serve as the foundation for applications like virtual sculpting, microstructure design and rapid prototyping, which usually deal with complex shape and topology model. The fast growing complexity of industrial models and the need to perform some operations repeatedly thereby necessitate an efficient processing system. However, since many fundamental geometric operations are compute-intensive, most commercial geometric kernels (e.g. Parasolid and ACIS), especially for freeform and highly-detailed complex models, require very high computational cost and do not work on such complex models. The purpose of this research is to exploit a solid modeler for freeform objects completely running on GPUs, which will greatly improve the efficiency of shape modeling. / A critical reason for such high computing intensity in operations is because they are performed on Boundary Representation (B-Rep). A new representation named Layered Depth Normal Images (LDNI) is introduced in this thesis to describe an object directly on GPU. LDNI is an extension of ray-representation which inherits the good properties of Boolean simplicity, localization, domain decoupling and the ease of parallel implementation, therefore provides a more feasible form than usual boundary representations. / Performing fundamental operations (such as Boolean operations, Minkowski sum, etc) are often time-consuming and prone to numerical problems when being applied on B-Rep model. This work develops several GPU-accelerated algorithms, including Boolean and general Minkowski sum. Our algorithms are carried out on image-based representation and thus are able to perform much faster than conventional approaches without arise any significant instability or robustness issues. / Algorithms have also been developed for converting B-Rep to LDNI and vice versa on GPU. Our sampling method makes use of rasterization to get the images for high efficiency and GPGPU libraries to convert them back to B-Rep. With these algorithms, the representations of models can be converted between this framework and other common CAD kernels. The framework also supports local refinement of coarse mesh, which is useful for reducing memory consumption while maintaining G¹ continuity. / Finally, the objective of this research is to provide a comprehensive framework for complex shape modeling problem. Several applications are demonstrated in using the GPU-based solid modeler, which shows great improvement in the efficiency compared with existing B-rep based systems. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Leung, Yuen Shan. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 148-159). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese. / Abstract --- p.i / Chinese Abstract --- p.iii / Acknowledgements --- p.iv / List of Figures --- p.ix / List of Tables --- p.xi / List of Publications --- p.xii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Contribution --- p.3 / Chapter 1.3 --- Organization --- p.4 / Chapter 2 --- Literature Review --- p.6 / Chapter 2.1 --- Exact Solid Modeling --- p.6 / Chapter 2.1.1 --- Solid Modeling Based on B-rep --- p.6 / Chapter 2.1.1.1 --- Data Structure --- p.7 / Chapter 2.1.1.2 --- Boolean Operation --- p.10 / Chapter 2.1.1.3 --- Problems --- p.11 / Chapter 2.1.2 --- Solid Modeling based on CSG --- p.11 / Chapter 2.1.2.1 --- Operations --- p.12 / Chapter 2.1.2.2 --- Comparison --- p.13 / Chapter 2.1.3 --- Boundary Space Partition Trees --- p.14 / Chapter 2.2 --- Approximate Solid Modeling --- p.16 / Chapter 2.2.1 --- Voxel representation --- p.16 / Chapter 2.2.2 --- Oct-tree representation --- p.18 / Chapter 2.2.3 --- Distance-Field --- p.20 / Chapter 2.2.4 --- Unorganized Point-Cloud --- p.22 / Chapter 2.3 --- Computational Intensive Operations --- p.23 / Chapter 2.3.1 --- Minkowski Sum --- p.23 / Chapter 2.3.2 --- Offset --- p.26 / Chapter 2.3.3 --- Sweeping --- p.29 / Chapter 2.4 --- Volumetric Representation to B-Rep Conversion --- p.32 / Chapter 2.5 --- Curved B-rep Generation on GPU --- p.33 / Chapter 3 --- Data Structure of Solid Modeling on GPU --- p.36 / Chapter 3.1 --- Layered Depth Normal Images --- p.36 / Chapter 3.2 --- Data Structure on GPU --- p.39 / Chapter 3.2.1 --- Encode Normal Vector --- p.41 / Chapter 3.2.2 --- Compactly Stored Data Structure --- p.42 / Chapter 4 --- Model Sampling in Image Space --- p.46 / Chapter 4.1 --- Introduction --- p.46 / Chapter 4.2 --- Prior Sampling Approaches --- p.48 / Chapter 4.2.1 --- Stencil Buffer --- p.50 / Chapter 4.2.2 --- Freepipe --- p.52 / Chapter 4.3 --- GPU-Accelerated Conservative Sampling --- p.53 / Chapter 4.3.1 --- Algorithm Overview --- p.54 / Chapter 4.3.2 --- Voxel Classification --- p.57 / Chapter 4.3.3 --- Fast Bit Checking --- p.60 / Chapter 4.3.4 --- MAX Blending for Depth Value Retrieval --- p.61 / Chapter 4.3.5 --- Implementation Detail --- p.62 / Chapter 4.4 --- Results and Discussion --- p.64 / Chapter 4.5 --- Applications --- p.67 / Chapter 5 --- Boolean Operations in Images Space --- p.69 / Chapter 5.1 --- Introduction --- p.69 / Chapter 5.2 --- GPU-Accelerated Boolean Operations --- p.70 / Chapter 5.2.1 --- Boolean Operations on shader --- p.70 / Chapter 5.2.2 --- Boolean Operations on CUDA --- p.71 / Chapter 5.3 --- Results and Discussion --- p.75 / Chapter 6 --- Minkowski Sum in Image Space --- p.77 / Chapter 6.1 --- Introduction --- p.77 / Chapter 6.2 --- Algorithm Based on Exterior Boundary Extraction --- p.78 / Chapter 6.3 --- GPU-Accelerated Minkowski Sum --- p.79 / Chapter 6.3.1 --- Minkowski Sums in Image Space Without Voids --- p.79 / Chapter 6.3.1.1 --- Algorithm Overview --- p.79 / Chapter 6.3.1.2 --- Implementation Issue --- p.80 / Chapter 6.3.1.3 --- Results and Performance --- p.81 / Chapter 6.3.2 --- Minkowski Sums with Inner Voids --- p.82 / Chapter 6.3.2.1 --- Algorithm Overview --- p.83 / Chapter 6.3.2.2 --- Convex Decomposition --- p.83 / Chapter 6.3.2.3 --- Pairwise Minkowski Sum --- p.85 / Chapter 6.3.2.4 --- Super-union in Image Space --- p.86 / Chapter 6.3.2.5 --- Results and Discussion --- p.90 / Chapter 6.3.2.6 --- Application --- p.93 / Chapter 7 --- Localized Construction of Curved Surfaces --- p.96 / Chapter 7.1 --- Local Construction of Curved Polygon --- p.98 / Chapter 7.1.1 --- Basic Construction Scheme --- p.98 / Chapter 7.1.1.1 --- Gregory Patch Interpolation --- p.98 / Chapter 7.1.1.2 --- Silhouette Curve Interpolation --- p.100 / Chapter 7.1.1.3 --- Cross-Tangent Function --- p.101 / Chapter 7.1.2 --- Property Analysis --- p.103 / Chapter 7.1.3 --- Discussions --- p.106 / Chapter 7.1.4 --- Algorithm for Generating N-Sided Polygons --- p.109 / Chapter 7.2 --- Flexible Shape Control --- p.111 / Chapter 7.2.1 --- Possibility of Extending the Basic Scheme --- p.111 / Chapter 7.2.2 --- Reorienting Silhouette Curve (Extended Scheme 1) --- p.111 / Chapter 7.2.3 --- Straight Silhouette (Extended Scheme 2) --- p.112 / Chapter 7.2.4 --- Crease (Extended Scheme 3) --- p.113 / Chapter 7.2.5 --- Silhouette Adjacent to Crease (Extended Scheme 4) --- p.113 / Chapter 7.2.6 --- Smooth Patch Bulging (Extended Scheme 5) --- p.114 / Chapter 7.2.7 --- Flat Surface (Extended Scheme 6) --- p.115 / Chapter 7.3 --- Implementation Details on GPU --- p.115 / Chapter 7.3.1 --- Refinement --- p.116 / Chapter 7.3.2 --- Position Mapping --- p.118 / Chapter 7.3.3 --- Normal Computation for Shading --- p.118 / Chapter 7.4 --- Results and Comparison --- p.119 / Chapter 8 --- B-rep Reconstruction on GPU --- p.124 / Chapter 8.1 --- Introduction --- p.124 / Chapter 8.2 --- B-rep Representation by Dual-Contouring --- p.125 / Chapter 8.3 --- GPU-Accelerated Dual-Contouring --- p.126 / Chapter 8.3.1 --- Algorithm Overview --- p.126 / Chapter 8.3.2 --- Implementation Issue --- p.129 / Chapter 8.4 --- Results and Discussion --- p.130 / Chapter 9 --- Applications --- p.133 / Chapter 9.1 --- Bone Graft --- p.133 / Chapter 9.2 --- Personalized Medical Treatment --- p.137 / Chapter 10 --- Conclusion --- p.139 / Chapter 10.1 --- Summary --- p.139 / Chapter 10.2 --- Future Work --- p.141 / Chapter A --- Appendix A: Examples and Results --- p.143 / Bibliography --- p.148

The integration of high-performance analog and digital circuits leads to an increasing need of new tools compatible for both the digital and analog parts. Unfortunately, the low acceptance of CAD tools in the analog domain presents a serious bottleneck to the fast realization of mixed-signal systems. Due to a higher sensitivity of the electrical performance to layout details, analog designs are much more complicated than digital ones. Process and temperature variations can introduce severe mismatches in devices that are designed to behave identically. These undesirable effects can be alleviated by a symmetric layout. Matching and symmetry in placement and routing in analog circuits are thus of immense importance. / In this thesis, we will present an effective layout method for analog circuits. We consider symmetry constraint, common centroid constraint, device merging and device clustering during the placement step. Symmetric routing will then be performed. In order to have successful routing, we will perform analog-based routability-driven adjustment during the placement process, taking into account for analog circuits that wires are not preferred to be layout on top of active devices. All these concepts were put together in our tool. Experimental results show that we can generate quality analog layout within minutes of time that passes the design rule check, layout-schematic verification and the simulation results are comparable to those of manual design, while a manual design will take a designer a couple of days to generate. / Xiao, Linfu. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 146-154). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract --- p.i / Acknowledgement --- p.ii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Analog Layout Problem --- p.2 / Chapter 1.1.1 --- Analog Circuit Design Flow --- p.3 / Chapter 1.1.2 --- An Example: μA741 Operational Amplifier --- p.5 / Chapter 1.1.3 --- Analog Layout Problem --- p.6 / Chapter 1.2 --- Thesis Contribution and Organization --- p.8 / Chapter 2 --- Background --- p.11 / Chapter 2.1 --- Analog Layout Basics --- p.11 / Chapter 2.1.1 --- Parasitic Effects --- p.12 / Chapter 2.1.2 --- Signal Coupling Effects --- p.13 / Chapter 2.1.3 --- Process Variation Effects --- p.15 / Chapter 2.2 --- Previous Analog Layout Automation Tools --- p.18 / Chapter 2.3 --- Previous Analog Layout Automation Approaches --- p.22 / Chapter 2.3.1 --- Device Generation --- p.23 / Chapter 2.3.2 --- Analog Placement --- p.25 / Chapter 2.3.3 --- Analog Routing --- p.37 / Chapter 3 --- System Overview --- p.45 / Chapter 3.1 --- System Flow Map --- p.45 / Chapter 3.1.1 --- Device Generation --- p.46 / Chapter 3.1.2 --- Analog Placement --- p.49 / Chapter 3.1.3 --- Analog Routing --- p.51 / Chapter 4 --- Analog Placement --- p.53 / Chapter 4.1 --- Introduction --- p.53 / Chapter 4.2 --- Symmetric Feasible Conditions on Sequence Pair --- p.55 / Chapter 4.2.1 --- Properties of Sequence Pair --- p.56 / Chapter 4.2.2 --- Symmetric Feasible Conditions --- p.58 / Chapter 4.3 --- Common Centroid Grid Placement --- p.69 / Chapter 4.3.1 --- Grid Placement Representation --- p.70 / Chapter 4.3.2 --- Common Centroid Feasible Conditions in Grid Sequence --- p.71 / Chapter 4.4 --- Methodology --- p.73 / Chapter 4.4.1 --- Handling Symmetry Constraints --- p.74 / Chapter 4.4.2 --- Device Merging --- p.75 / Chapter 4.4.3 --- Device Clustering --- p.77 / Chapter 4.4.4 --- Enhanced Common Centroid Placement --- p.78 / Chapter 4.4.5 --- Placement Adjustment for Symmetry Groups --- p.82 / Chapter 4.4.6 --- Congestion Aware Placement Expansion --- p.86 / Chapter 4.4.7 --- Types of Moves --- p.87 / Chapter 4.4.8 --- Annealing Schedule and Cost Function --- p.88 / Chapter 5 --- Analog Routing --- p.90 / Chapter 5.1 --- Introduction --- p.90 / Chapter 5.2 --- Methodology --- p.91 / Chapter 5.2.1 --- Symmetry Routing --- p.94 / Chapter 5.2.2 --- Practical Concerns --- p.97 / Chapter 6 --- Layer Assignment --- p.106 / Chapter 6.1 --- Introduction --- p.106 / Chapter 6.1.1 --- Problem Formulation --- p.108 / Chapter 6.1.2 --- Previous Works --- p.109 / Chapter 6.1.3 --- Background --- p.111 / Chapter 6.2 --- Methodology --- p.114 / Chapter 6.2.1 --- Global Conflict-Continuation Graph Construction --- p.114 / Chapter 6.2.2 --- The Modified Two-layer Layer Assignment Scheme --- p.116 / Chapter 6.2.3 --- Stacked Via Problem and Crosstalk --- p.120 / Chapter 6.2.4 --- Max-Cut for planar graph --- p.121 / Chapter 7 --- Experimental Results --- p.128 / Chapter 7.1 --- Results of Analog Placement --- p.129 / Chapter 7.2 --- Results of Layer Assignment --- p.133 / Chapter 7.3 --- Simulation Results --- p.134 / Bibliography --- p.136

This thesis presents a study of an ancient Chinese timber structure- the main hall of the Foguang temple built in China in the Tang Dynasty (857), which is regarded as one of the most important temples in that period. The research represents a detailed digital model of the structural timber components and their connectivity. The research questions are: - Firstly, how to identify and represent the structural components, and the ways they are assembled. This is not covered in the few previous studies of the temple, which just offered brief introductions and general descriptions of the construction of the timber structure. - Secondly, how to create a digital model for such a structure where there is insufficient or incompatible information. These are common issues that arise in the simulation and representation of historic architecture. The outcome of the research is the presentation of a digital model that is much more detailed than previously existing representations. During the process, two concepts were developed and adopted: - Firstly, the concept of "building an ideal model". Rather than seeking the representation of the timber structure as built, the notion outlined in this thesis is to create an ideal digital model according to the vocabulary of structural components and the predefined spatial relations of their assembly connectivity. - Secondly, the concept of "simplest adaptation". When choosing from a number of reasonable hypotheses about a component or assembly detail, it is assumed to be the simplest possible adaptation of an already accepted component or assembly detail. The thesis is organized as followings: Chapter 1: an introduction to the research on ancient Chinese architecture. Chapter 2: a review of the computer simulation and representation of historic architecture. Chapter 3: a discussion about the methodology on the concept of "building an ideal model", and the methodology for modelling when there is a lack of information. Chapter 4: a record of the digital modelling process. Chapter 5: discussions on and conclusions of the research. The thesis has an accompanying CD which contains the representation information, including: - A 2D 'Flash' presentation that shows the brief contents of the research. - 3D animations that represent in detail the timber structure and the assembly process. - A database that represents the structural components and their relations. / Thesis (M.Arch.)--School of Architecture, Landscape Architecture & Urban Design, 2005.

The sketching software developed in this thesis, is aimed to serve as an intelligent design tool for the conceptual design stage of the mechanical design process. This sketching software, Sketch Pad for Windows, closely mimics the traditional paper-and-pencil sketching environment by allowing the user to sketch freely on the computer screen using a mouse. The recognition algorithm built into the application replaces the sketch stroke with the exact CAD entity. Currently, the recognition of two-dimensional design primitives such as lines, circles and arcs has been addressed. Since manufacturing requires that the design concepts be detailed, sketches need to be refined as detailed drawings. This process of carrying design data from the conceptual design stage into the detail designing stage is achieved with the help of a convertor that converts the sketch data into DesignView (a variational CAD software). Currently, only geometrical information is transferred from the sketching software into DesignView. The transparent graphical user interface built into this sketching system challenges the hierarchial and regimental user interface built into current CAD software. / Graduation date: 1995

The design of a pop-up book or card has hitherto been labour intensive with tasks of trials and errors. The constructions of collapsible pop-up structures can be demanding and inefficient without adequate knowledge of their geometric properties. This paper examines the properties of creases in 90° pop-up structures. A 90° pop-up structure is one that erects fully when two adjacent base pages, on which it sits, are opened to a right angle. In particular, we define a boundary region for creating 90° pop-ups. Similarly, paper folds are able to achieve pop-up effects and can be integrated with 90° pop-up constructions. The development of these pop-up structures can be represented graphically. Through this study, a fundamental foundation for pop-up topology and geometry is built. This foundation would be vital for understanding the applications of pop-up making techniques. The mathematical relationships devised would be useful for developing computer-enhanced pop-up design. / Singapore-MIT Alliance (SMA)

Here we search for the curve which has the smallest integral of the square of curvature, while passing through two given points with given orientation. This is the true shape of a spline used in lofting. In computer-aided design, curves have been sought which maximize "smoothness". The curve discussed here is the one arising in this way from a commonly used measure of smoothness. The human visual system may use such a curve when it constructs a subjective contour.

This manual describes the Design Procedure Language (DPL) for LSI design. DPL creates and maintains a representation of a design in a hierarchically organized, object-oriented LISP data-base. Designing in DPL involves writing programs (Design Procedures) which construct and manipulate descriptions of a project. The programs use a call-by-keyword syntax and may be entered interactively or written by other programs. DPL is the layout language for the LISP-based Integrated Circuit design system (LISPIC) being developed at the Artificial Intelligence Laboratory at MIT. The LISPIC design environment will combine a large set of design tools that interact through a common data-base. This manual is for prospective users of the DPL and covers the information necessary to design a project with the language. The philosophy and goals of the LISPIC system as well as some details of the DPL data-base are also discussed.

By enhancing a real scene with computer generated objects, Augmented Reality (AR), has proven itself as a valuable Human-Computer Interface (HCI) in numerous application areas such as medical, military, entertainment and manufacturing. It enables higher performance of on-site tasks with seamless presentation of up-to-date, task-related information to the users during the operation. AR has potentials in design because the current interface provided by Computer-aided Design (CAD) packages is less intuitive and reports show that the presence of physical objects help design thinking and communication. This research explores the use of AR to improve the efficiency of a design process, specifically in mechanical design. / Singapore-MIT Alliance (SMA)

Thesis (M.S.)--Brigham Young University. Dept. of Mechanical Engineering, 2005. / Includes bibliographical references (p. 131-139).

Thesis (Ph. D.)--University of Hong Kong, 2006. / Title proper from title frame. Also available in printed format.