<p> Firewalls, packet filters placed at the boundary of a network in order to screen incoming packets of traffic (and discard any undesirable packets), are a prominent component of network security. In this dissertation, we make several contributions to the study of firewalls.</p><p> 1. Current algorithms for verifying the correctness of firewall policies use <i>O</i>(<i>n^d</i>) space, where <i>n</i> is the number of rules in the firewall (several thousand) and <i>d</i> the number of fields in a rule (about five). We develop a fast probabilistic firewall verification algorithm, which runs in time and space <i>O</i>(<i>nd</i>), and determines whether a firewall <i> F</i> satisfies a property <i>P.</i> The algorithm is provably correct in several interesting cases&mdash;notably, for every instance where it states that <i>F</i> does not satisfy <i>P</i>&mdash;and the overall probability of error is extremely small, of the order of .005%. </p><p> 2. As firewalls are often security-critical systems, it may be necessary to verify the correctness of a firewall with no possibility of error, so there is still a need for a fast deterministic firewall verifier. In this dissertation, we present a deterministic firewall verification algorithm that uses only <i> O</i>(<i>nd</i>) space.</p><p> 3. In addition to correctness, optimizing firewall performance is an important issue, as slow-running firewalls can be targeted by denial-of-service attacks. We demonstrate in this dissertation that in fact, there is a strong connection between firewall verification and detection of redundant rules; an algorithm for one can be readily adapted to the other task. We suggest that our algorithms for firewall verification can be used for firewall optimization also.</p><p> 4. In order to help design correct and efficient firewalls, we suggest two metrics for firewall complexity, and demonstrate how to design firewalls as a battery of simple firewall modules rather than as a monolithic sequence of rules. We also demonstrate how to convert an existing monolithic firewall into a modular firewall. We propose that modular design can make firewalls easy to design and easy to understand.</p><p> Thus, this dissertation covers all stages in the life cycle of a firewall&mdash;design, testing and verification, and analysis&mdash;and makes contributions to the current state of the art in each of these fields.</p>

<p>Diagnosing performance problems in modern datacenters and distributed systems is challenging, as the root cause could be contained in any one of the system's numerous components or, worse, could be a result of interactions among them. As distributed systems continue to increase in complexity, diagnosis tasks will only become more challenging. There is a need for a new class of diagnosis techniques capable of helping developers address problems in these distributed environments. </p><p> As a step toward satisfying this need, this dissertation proposes a novel technique, called <i>request-flow comparison,</i> for automatically localizing the sources of <i>performance changes</i> from the myriad potential culprits in a distributed system to just a few potential ones. Request-flow comparison works by contrasting the workflow of how individual requests are serviced within and among every component of the distributed system between two periods: a non-problem period and a problem period. By identifying and ranking performance-affecting changes, request-flow comparison provides developers with promising starting points for their diagnosis efforts. Request workflows are obtained with less than 1% overhead via use of recently developed end-to-end tracing techniques. </p><p> To demonstrate the utility of request-flow comparison in various distributed systems, this dissertation describes its implementation in a tool called Spectroscope and describes how Spectroscope was used to diagnose real, previously unsolved problems in the Ursa Minor distributed storage service and in select Google services. It also explores request-flow comparison's applicability to the Hadoop File System. Via a 26-person user study, it identifies effective visualizations for presenting request-flow comparison's results and further demonstrates that request-flow comparison helps developers quickly identify starting points for diagnosis. This dissertation also distills design choices that will maximize an end-to-end tracing infrastructure's utility for diagnosis tasks and other use cases. </p>

<p> Object Oriented Programming (OOP) is a contemporary favorite method of programming. OOP provides better flexibility, source codes are more organized and systematized, and it enables a group of developers to easily work with each other. Nevertheless, a poorly designed system will not only defeat the intention of coding with OOP, but also will make the software extremely difficult to maintain.</p><p> Refactoring is a powerful way to improve existing code. It only changes the structure of the source code without changing its functionality. Manually refactoring larger systems not only consumes large amounts of time and money, but it also happens to be incredibly inaccurate. As a result, quick and easy refactoring with partial automation is extensively discussed in the software realm.</p><p> This thesis presents algorithms for implementing nine refactorings that work on the fly for JAVA source code. The refactorings algorithms are implemented in a stepwise manner by initially selecting the source code portion for refactoring, and by choosing the correct refactoring method, and then programmatically changing the selected source code to achieve refactoring.</p>

<p> Computer emulations, simulating real or imagined computer systems, are a valuable tool to quickly gain understanding of computer architecture and software. Existing computer emulation systems offer useful but limited visualization and interaction. This paper addresses improving usability of pedagogical computer emulator interfaces with the application of published design principles informed by research into visuospatial ability. The results include a survey of promising techniques addressing similar problems and suggestions for application. Along with supporting work extending a publicly available Java-based PC emulator to enable use of the popular Processing visualization development environment, this provides a well-developed design and implementation framework for future improvements by interested parties.</p>

<p> The explosive mobile data growth needs more spectrum to accommodate the traffic. Existing policy of exclusive spectrum access has made today's spectrum both over-controlled and underutilized. One possibility to improve spectrum efficiency is via dynamic spectrum sharing, which has the potential to release a large percentage of underutilized spectrum. </p><p> Cognitive radio is one of the most promising technologies to facilitate dynamic spectrum sharing. Yet, there exist many problems for cognitive radio to support multimedia communications. This dissertation advances the concept of <i>&ldquo;spectrum aware&rdquo;</i> for cognitive-radio based wireless multimedia communication system. We interpret spectrum awareness in a broad way which includes spectrum sensing, spectrum effectiveness and spectrum efficiency. In particular, we have made the following contributions in this dissertaion: </p><p> &bull; We design and implement RECOG, a cognitive radio (CR) system that improves conventional CR with a smart sensing, fast backup channel searching and QoS managing. The proposed system is the first fully-fledge CR system that can supports real-time applications such as video chat. </p><p> &bull; We design and implement PINOKIO, a system that monitors spectrum usage and improves spectrum efficiency in frequency-agile WiFi networks. </p><p> &bull; We design and implement FAVICS, a frequency-aware video communication system that leverages the nature of unequal error protection (UEP) in frequency diversity for wireless streaming without modifying existing wireless PHY, and improve the peak signal-to-noise ratio (PSNR) of video streaming by 5&sim;10 dB.</p>

<p> Hardware accelerators provide a rare opportunity to achieve orders-of-magnitude performance and power improvements with customized circuit designs.</p><p> Many forms of hardware acceleration exist&mdash;attributes and trade-offs of each approach is discussed. Single-algorithm accelerators, which maximize efficiency gains through maximum specialization, are one such approach. By combining many of these into a many-accelerator system, high specialization is possible with fewer specialization limits.</p><p> The development of one such single-algorithm hardware accelerator for managing compressed Bloom filters in wireless sensor networks is presented. Results from the development of the accelerator highlight scalability deficiencies in the way accelerators are currently integrated into processors, and that the majority of accelerator area is consumed by generic SRAM memory rather than algorithm-specific logic.</p><p> These results motivate development of the accelerator store, a system architecture designed for the needs of many-accelerator systems. In particular, the accelerator store improves inter-accelerator communication and includes support for sharing accelerator SRAM memories. Using a security application as an example, the accelerator store architecture is able to reduce total processor area by 30% with less than 1% performance overhead.</p><p> Using the accelerator store as a base, the ShrinkFit framework allows accelerators to grow and shrink, to achieve accelerated performance within small FPGA budgets and efficiently expand for more performance when larger FPGA budgets are available. The ability to resize accelerators is particularly useful for hybrid systems combining GP-CPUs and FPGA resources, in which applications may deploy accelerators to a shared FPGA fabric. ShrinkFit performance overheads for small and large FPGA resources are found to be low using a robotic bee brain workload and FPGA prototype.</p><p> Finally, future directions are briefly discussed along with details about the production of the robotic bee helicopter brain prototype.</p>

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Emerging processor technologies are becoming commercially available that make multi-processor capabilities affordable for use in a large number of computer systems. Increasing power consumption by this next generation of processors is a growing concern as the cost of operating such systems continues to increase. It is important to understand the characteristics of these emerging technologies in order to enhance their performance. By understanding the characteristics of high performance computing workloads on real systems, the overall efficiency with which such workloads are executed can be increased. In addition, it is important to determine the best trade-off between system performance and power consumption using the variety of system configurations that are possible with these new technologies. This thesis seeks to provide a comprehensive presentation of the performance characteristics of several real commercially available simultaneous-multithreading multi-processor architectures and provide recommendations to improve overall system performance. As well, it will provide solutions to reduce the power consumption of such systems while minimizing the performance impact of these techniques on the system. The results of the research conducted show that the new scheduler proposed in this thesis is capable of providing significant increases in efficiency for traditional and emerging multi-processor technologies. These findings are confirmed using real system performance and power measurements. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2007-08-16 16:06:15.414

A thorough review of selected results on the logical aspects of regular languages includes the theorem of Büchi on monadic second order logic over strings, a characterization of FO[<l and the theorem of 1. Simon. With the help of the Ehrenfeucht-Fraïssé Game we show that :J(k+ltsentences of FO[<1 cannot be expressed as a boolean combination of :J(ktsentences. Block product of finite monoids is used to analyze languages defined by the boolean closure of the 2::2-sentences. Positive varieties and the Mal'cev product are introduced and 2::n +l n IIn+l is shown to be equal to the unambiguous polynomial closure of the nth level of the Straubing-Thérien hierarchy. In particular, 2:: 2 n II2 = VA, where VA is the smallest variety of languages closed under the unambiguous product. / Nous proposons un aperçu complet de résultats choisis concernant les aspects logiques des langages réguliers incluant le théorème de Büchi sur la logique monadique de second ordre sur les chaînes de caractères, la caractérisation de FO[<J et le théorème de 1. Simon. Grâce au jeu de Ehrenfeucht-Fraïssé, nous démontrons que, dans FO[<J, les énoncés logiques 3(k+1) ne peuvent être exprimés comme une combinaison booléene d'énoncés 3(k). Nous utilisons le produit bloc de monoïdes finis pour analyser les langages définis par la fermeture booléene des énoncés 2:: 2 • Nous présentons également les variétés positives et le produit de Mal'cev et montrons que 2::n +1 n IIn+1 est égal à la fermeture polynomiale non-ambigue du nième niveau de la hiérarchie de StraubingThérien. En particulier, 2:: 2 n II2 = VA, où VA est la plus petite variété de langages fermée sous le produit non-ambigu fr

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