Fault diagnosis plays an important role in improving the circuit design process and the manufacturing yield. With the increasing number of gates in modern circuits, determining the source of failure in a defective circuit is becoming more and more challenging. In this research, we present an efficient effect-cause diagnosis framework for combinational VLSI circuits. The framework consists of three stages to obtain an accurate and reasonably precise diagnosis. First, an improved critical path tracing algorithm is proposed to identify an initial suspect list by backtracing from faulty primary outputs toward primary inputs. Compared to the traditional critical path tracing approach, our algorithm is faster and exact. Second, a novel probabilistic ranking model is applied to rank the suspects so that the most suspicious one will be ranked at or near the top. Several fast filtering methods are used to prune unrelated suspects. Finally, to refine the diagnosis, fault simulation is performed on the top suspect nets using several common fault models. The difference between the observed faulty behavior and the simulated behavior is used to rank each suspect. Experimental results on ISCAS85 benchmark circuits show that this diagnosis approach is efficient both in terms of memory space and CPU time and the diagnosis results are accurate and reasonably precise.

La croissance rapide dans le domaine des semi-conducteurs fait que les circuits digitaux deviennent de plus en plus complexes. La capacité à identifier la cause réelle d'une défaillance dans un circuit digital est donc critique. Le diagnostic logique est une procédure qui permet de localiser une erreur observée dans un circuit fautif, l'analyse de défaillance peut être ensuite appliquée pour déterminer la cause réelle de cette erreur. Un diagnostic efficace et précis est donc fondamental pour améliorer les résultats de l'analyse de défaillance et augmenter éventuellement le rendement de production."Effet à Cause" et "Cause à Effet" sont deux approches classiques pour le diagnostic logique. Ce diagnostic fournit une liste de suspects au niveau porte logique. Cependant, cette approche n'est pas précise dans le cas où le défaut est localisé à l'intérieur de la cellule logique.Dans cette thèse, nous proposons une nouvelle méthode de diagnostic intra-cell basé sur l'approche "Effet à Cause" pour améliorer la précision de la localisation de défaut au niveau transistor. L'approche proposée utilise l'algorithme CPT (Traçage de chemins critiques) appliqué au niveau transistor. Pour chaque cellule suspecte, nous appliquons un CPT avec les vecteurs de test fautifs. Le résultat obtenu est une liste de suspects préliminaires. Chaque suspect peut être un noeud (G, S, D) de transistor. Par la suite, nous appliquons un CPT avec les vecteurs de test non-fautifs pour minimiser la liste de suspects. La méthode proposée donne la localisation précise du défaut pour une erreur observée. Par ailleurs, la méthode est indépendante du modèle de faute invoqué. / The rapid growth in semiconductor field results in an increasing complexity of digital circuits. The ability to identify the root cause of a failing digital circuit is becoming critical for defect localization. Logic diagnosis is the process of isolating the source of observed errors in a defective circuit, so that a physical failure analysis can be performed to determine the root cause of such errors. Effective and precise logic diagnosis is crucial to speed up the failure analysis and eventually to improve the yield.“Effect-Cause” and “Cause-Effect” are the two classical approaches for logic diagnosis. Logic diagnosis provides a list of gates as suspects. However, this approach may not leads to accurate results in the case of the defect is inside a gate.We propose a new intra-cell diagnosis method based on “Effect-Cause” approach to improve the defect localization accuracy at transistor level. The proposed approach exploits the CPT (Critical Path Tracing) applied at transistor level. For each suspected cell, we apply the CPT for every given failing test vector. The result is a preliminary list of candidates. Each candidate can be a net or a transistor drain, gate or source. After that, we apply the CPT for each passing test vector in order to narrow down the the list of candidates. The proposed method gives precise localization of the root cause of the observed errors. Moreover, it does not require the explicit use of a fault model.

Optical shrink for process migration, manufacturing process variation and dynamic voltage control leads to clock skew as well as path delay variation in a manufactured chip. Since such variations are difficult to predict in pre-silicon phase, tunable clock buffers have been used in several microprocessor designs. The buffer delays are tuned to improve maximum operating clock frequency of a design. This however shifts the burden of finding tuning settings for individual clock buffers to the test process. In this project, we describe a process of using tester measurements to determine the settings of the tunable buffers for recovery of performance lost due to process variations. Then we study the impact of positioning of tunable buffers in the clock tree. In course of our study it was observed that the greatest benefit from tunable buffer placement can be derived, when the clock tree is synthesized with future tuning considerations. Accordingly, we present a clock tree synthesis procedure which offers very good mitigation against process variation, as borne out by the results. The results show that without any design intervention, an average improvement of 9% is achieved by our tuning system. However, when the clock tree is synthesized based on static timing information with tuning buffer placement considerations, much larger performance improvement is possible. In one example, performance improved by as much as 18%.