Le présent travail porte sur la modélisation et l’implémentation un crypto-processeur reconfigurable capable de garantir le niveau de sécurité exigé. L’étude de la résistance du crypto-système étudié aux différents types d’attaques (statistiques, linéaires et différentielles) peut nous mettre sur la trace de possibles failles, d’en extraire les points faibles et de proposer les contres mesures adéquates. C’est ainsi qu’on a pu proposer des approches de correction afin d’améliorer la robustesse de l’algorithme de cryptage symétrique par blocs. Pour cet effet, on a proposé un flot de conception optimisé pour la modélisation, la vérification et la correction des primitives cryptographiques. Mais la contribution majeure du présent travail fût l’exploitation des propriétés de la théorie de chaos. Pour la conception du crypto-processeur proposé, on a fait appel aux avantages de la modélisation à haut niveau. On a proposé d'utiliser les deux niveaux d'abstraction CABA et TLM. L’utilisation simultanée de ces deux niveaux est possible par le biais du niveau ESL, ce qui garantit de minimiser d’une part l’effort permettant de spécifier les fonctionnalités demandées et d’autre part de négliger les détails inutiles au niveau haut de la conception. / Regarding the increasing complexity of cryptographic devices, testing their security level against existing attacks requires a fast simulation environment. The Advanced Encryption Standard (AES) is widely used in embedded systems in order to secure the sensitive data. Still, some issues lie in the used key and the S-BOX. The present work presents a SystemC implementation of a chaos-based crypto-processor for the AES algorithm.The design of the proposed architecture is studied using the SystemC tools. The proposed correction approach exploits the chaos theory properties to cope with the defaulting parameters of the AES algorithm. Detailed experimental results are given in order to evaluate the security level and the performance criteria. In fact, the proposed crypto- system presents numerous interesting features, including a high security level, a pixel distributing uniformity, a sufficiently large key-space with improved key sensitivity, and acceptable speed.

This thesis study presents design and SystemC implementation of a Crypto Processor for Advanced Encryption Standard (AES), Data Encryption Standard (DES) and Triple DES (TDES) algorithms. All of the algorithms are implemented in single architecture instead of using separate architectures for each of the algorithm. There is an Instruction Set Architecture (ISA) implemented for this Crypto Processor and the encryption and decryption of algorithms can be performed by using the proper instructions in the ISA. A permutation module is added to perform bit permutation operations, in addition to some basic structures of general purpose micro processors. Also the Arithmetic Logic Unit (ALU) structure is modified to process some crypto algorithm-specific operations. The design of the proposed architecture is studied using SystemC. The architecture is implemented in modules by using the advantages of SystemC in modular structures. The simulation results from SystemC are analyzed to verify the proposed design. The instruction sets to implement the crypto algorithms are presented and a detailed hardware synthesis study has been carried out using the tool called SystemCrafter.

Πολλά πρότυπα ασφαλούς επικοινωνίας, όπως το secure shell (SSH), IP security (IPsec), καθώς και διάφορες μορφές κρυπτογράφησης e-mail δημιουργήθηκαν για να προστατεύουν τις πληροφορίες κατά τη μεταφορά, διασφαλίζοντας το κανάλι επικοινωνίας. Ωστόσο, γίνεται αντιληπτό ότι τα δεδομένα σε αποθήκευση (data at rest) είναι επίσης ευάλωτα σε επιθέσεις και πρέπει να προστατευτούν. Το πρότυπο IEEE P1619, το οποίο έχει προταθεί από το IEEE, προσδιορίζει τα βασικά στοιχεία μιας αρχιτεκτονικής, η οποία παρέχει ασφάλεια σε sector-level-random-access διαμοιραζόμενα μέσα αποθήκευσης, επιλέγοντας ως το καταλληλότερο mode λειτουργίας το Electronic codebook (ECB). Βασικό μειονέκτημα αυτού του τρόπου κρυπτογράφησης είναι ότι κατά το ECB mode το ίδιο plaintext παράγει πάντα (κρυπτογραφείται) το ίδιο ciphertext, δημιουργώντας την ανάγκη για συχνή αλλαγή στο συμμετρικό κλειδί. Μια τέτοια πρακτική όμως δεν θα αποδίδει λόγω του απαιτούμενου χρόνου για την επέκταση των νέων κλειδιών. Το πρόβλημα αυτό αντιμετωπίζει το IEEE P1619, κάνοντας χρήση της θέσης (location) των δεδομένων ως την επιθυμητή μεταβαλλόμενη τιμή κλειδιού, εφαρμόζοντας block-cipher αλγόριθμους κρυπτογράφησης. Το νέο αυτό πρότυπο έχει προσελκύσει την προσοχή εταιριών, ως μια καλή λύση για τις απαιτήσεις των καταναλωτών για υψηλό επίπεδο ασφάλειας των δεδομένων σε συσκευές αποθήκευσης. Πρόσφατες ερευνητικές εργασίες ερευνούν ή/και παρουσιάζουν διάφορες αρχιτεκτονικές για την υλοποίηση του προτύπου σε υλικό (hardware), με στόχο την υιοθέτησή τους σε μελλοντικά προϊόντα. Οι προτεινόμενες προσεγγίσεις στοχεύουν στην αξιοποίηση είτε πόρων του υπολογιστή (προσεγγίσεις λογισμικού) είτε ειδικού σκοπού υλικού, στοχεύοντας σε διαφορετικές απαιτήσεις, ανάλογων της εφαρμογής. Η εργασία αυτή επικεντρώνεται σε ένα Narrow-block Tweak-able σχήμα κρυπτογράφησης (XTS-AES) και διερευνά διάφορες αρχιτεκτονικές που προσφέρουν μια ποικιλία χαρακτηριστικών. Αυτή είναι η πρώτη προσπάθεια διερεύνησης αρχιτεκτονικών προσεγγίσεων (υφιστάμενων και προτεινόμενων), με σκοπό να αναδειχθεί η καταλληλότερη αρχιτεκτονική για μια ποικιλία εφαρμογών. Το βασικό χαρακτηριστικό των προτεινόμενων αρχιτεκτονικών είναι η μεγιστοποίηση της αξιοποίησης των πόρων που υλοποιούν το IEEE P1619, ώστε να επιτευχθεί η υψηλότερη απόδοση, λαμβάνοντας υπόψη διάφορα κριτήρια σχεδιασμού, όπως είναι η υψηλή ταχύτητα, η μικρή επιφάνεια, το χαμηλό κόστος και η σχεδιαστική πολυπλοκότητα. / A standard for the protection of data in shared storage media has been proposed by IEEE, the IEEE P1619. It specifies the fundamental elements of an architecture that provides security in block-based shared storage media applying block-cipher encryption algorithms to blocks of data. The newly presented standard has attracted the attention of the market vendors, as a good solution to the demands of the consumers for higher security levels in storage devices. The manufacturers have already developed future platforms based on IEEE P1619. Recent research works introduced various approaches targeting their adoption in future products. The proposed approaches are aiming to exploit either computer resources (software approaches) or special purpose hardware. This work focuses on the Narrow-block Tweakable encryption scheme (XTS-AES transform) and explores various architectures offering a variety of characteristics to the final implementation. This is the first, to the authors knowledge, attempt to explore the various architecture approaches that have been proposed until now and additionally introduce new ones, with an aim to highlight the appropriate architecture for a variety of applications. The key feature of the proposed architectures is parallelism, with respect to data block processing. The target is to exploit in full the resources of the core(s) implementing the IEEE P1619 and achieve the highest performance, respecting various design criteria as low cost, and/or design complexity. Basic details regarding IEEE P1619 and its dominant unit (the XTS-AES transform) are offered, a summary of previous works is presented and several issues are considered for potential optimization of the system architecture. Novel architectures are introduced, exploring time-scheduling of the processes to be performed and the characteristics of the various architectures are analyzed and compared.

Architectures of cryptographic processors and coprocessors are often vulnerable to different kinds of attacks, especially those targeting the disclosure of encryption keys. It is well known that manipulating confidential keys by the processor as ordinary data can represent a threat: a change in the program code (malicious or unintentional) can cause the unencrypted confidential key to leave the security area. This way, the security of the whole system would be irrecoverably compromised. The aim of our work was to search for flexible and reconfigurable hardware architectures, which can provide high security of confidential keys during their generation, storage and exchange while implementing common symmetric key cryptographic modes and protocols. In the first part of the manuscript, we introduce the bases of applied cryptography and of reconfigurable computing that are necessary for better understanding of the work. Second, we present threats to security of confidential keys when stored and processed within an embedded system. To counteract these threats, novel design rules increasing robustness of cryptographic processors and coprocessors against software attacks are presented. The rules suggest separating registers dedicated to key storage from those dedicated to data storage: we propose to partition the system into the data, cipher and key zone and to isolate the zones from each other at protocol, system, architectural and physical levels. Next, we present a novel HCrypt crypto-processor complying with the separation rules and thus ensuring secure key management. Besides instructions dedicated to secure key management, some additional instructions are dedicated to easy realization of block cipher modes and cryptographic protocols in general. In the next part of the manuscript, we show that the proposed separation principles can be extended also to a processor-coprocessor architecture. We propose a secure crypto-coprocessor, which can be used in conjunction with any general-purpose processor. To demonstrate its flexibility, the crypto-coprocessor is interconnected with the NIOS II, MicroBlaze and Cortex M1 soft-core processors. In the following part of the work, we examine the resistance of the HCrypt cryptoprocessor to differential power analysis (DPA) attacks. Following this analysis, we modify the architecture of the HCrypt processor in order to simplify its protection against side channel attacks (SCA) and fault injection attacks (FIA). We show that by rearranging blocks of the HCrypt processor at macroarchitecture level, the new HCrypt2 processor becomes natively more robust to DPA and FIA. Next, we study possibilities of dynamically reconfiguring selected parts of the processor - crypto-coprocessor architecture. The dynamic reconfiguration feature can be very useful when the cipher algorithm or its implementation must be changed in response to appearance of some vulnerability. Finally, the last part of the manuscript is dedicated to thorough testing and optimizations of both versions of the HCrypt crypto-processor. Architectures of crypto-processors and crypto-coprocessors are often vulnerable to software attacks targeting the disclosure of encryption keys. The thesis introduces separation rules enabling crypto-processor/coprocessors to support secure key management. Separation rules are implemented on novel HCrypt crypto-processor resistant to software attacks targetting the disclosure of encryption keys

Les architectures des processeurs et coprocesseurs cryptographiques se montrent fréquemment vulnérables aux différents types d’attaques ; en particulier, celles qui ciblent une révélation des clés chiffrées. Il est bien connu qu’une manipulation des clés confidentielles comme des données standards par un processeur peut être considérée comme une menace. Ceci a lieu par exemple lors d’un changement du code logiciel (malintentionné ou involontaire) qui peut provoquer que la clé confidentielle sorte en clair de la zone sécurisée. En conséquence, la sécurité de tout le système serait irréparablement menacée. L’objectif que nous nous sommes fixé dans le travail présenté, était la recherche d’architectures matérielles reconfigurables qui peuvent fournir une sécurité élevée des clés confidentielles pendant leur génération, leur enregistrement et leur échanges en implantant des modes cryptographiques de clés symétriques et des protocoles. La première partie de ce travail est destinée à introduire les connaissances de base de la cryptographie appliquée ainsi que de l’électronique pour assurer une bonne compréhension des chapitres suivants. Deuxièmement, nous présentons un état de l’art des menaces sur la confidentialité des clés secrètes dans le cas où ces dernières sont stockées et traitées dans un système embarqué. Pour lutter contre les menaces mentionnées, nous proposons alors de nouvelles règles au niveau du design de l’architecture qui peuvent augmenter la résistance des processeurs et coprocesseurs cryptographiques contre les attaques logicielles. Ces règles prévoient une séparation des registres dédiés à l’enregistrement de clés et ceux dédiés à l’enregistrement de données : nous proposons de diviser le système en zones : de données, du chiffreur et des clés et à isoler ces zones les unes des autres au niveau du protocole, du système, de l’architecture et au niveau physique. Ensuite, nous présentons un nouveau crypto-processeur intitulé HCrypt, qui intègre ces règles de séparation et qui assure ainsi une gestion sécurisée des clés. Mises à part les instructions relatives à la gestion sécurisée de clés, quelques instructions supplémentaires sont dédiées à une réalisation simple des modes de chiffrement et des protocoles cryptographiques. Dans les chapitres suivants, nous explicitons le fait que les règles de séparation suggérées, peuvent également être étendues à l’architecture d’un processeur généraliste et coprocesseur. Nous proposons ainsi un crypto-coprocesseur sécurisé qui est en mesure d’être utilisé en relation avec d’autres processeurs généralistes. Afin de démontrer sa flexibilité, le crypto-coprocesseur est interconnecté avec les processeurs soft-cores de NIOS II, de MicroBlaze et de Cortex M1. Par la suite, la résistance du crypto-processeur par rapport aux attaques DPA est testée. Sur la base de ces analyses, l’architecture du processeur HCrypt est modifiée afin de simplifier sa protection contre les attaques par canaux cachés (SCA) et les attaques par injection de fautes (FIA). Nous expliquons aussi le fait qu’une réorganisation des blocs au niveau macroarchitecture du processeur HCrypt, augmente la résistance du nouveau processeur HCrypt2 par rapport aux attaques de type DPA et FIA. Nous étudions ensuite les possibilités pour pouvoir reconfigurer dynamiquement les parties sélectionnées de l’architecture du processeur – crypto-coprocesseur. La reconfiguration dynamique peut être très utile lorsque l’algorithme de chiffrement ou ses implantations doivent être changés en raison de l’apparition d’une vulnérabilité Finalement, la dernière partie de ces travaux de thèse, est destinée à l’exécution des tests de fonctionnalité et des optimisations stricts des deux versions du cryptoprocesseur HCrypt / Architectures of cryptographic processors and coprocessors are often vulnerable to different kinds of attacks, especially those targeting the disclosure of encryption keys. It is well known that manipulating confidential keys by the processor as ordinary data can represent a threat: a change in the program code (malicious or unintentional) can cause the unencrypted confidential key to leave the security area. This way, the security of the whole system would be irrecoverably compromised. The aim of our work was to search for flexible and reconfigurable hardware architectures, which can provide high security of confidential keys during their generation, storage and exchange while implementing common symmetric key cryptographic modes and protocols. In the first part of the manuscript, we introduce the bases of applied cryptography and of reconfigurable computing that are necessary for better understanding of the work. Second, we present threats to security of confidential keys when stored and processed within an embedded system. To counteract these threats, novel design rules increasing robustness of cryptographic processors and coprocessors against software attacks are presented. The rules suggest separating registers dedicated to key storage from those dedicated to data storage: we propose to partition the system into the data, cipher and key zone and to isolate the zones from each other at protocol, system, architectural and physical levels. Next, we present a novel HCrypt crypto-processor complying with the separation rules and thus ensuring secure key management. Besides instructions dedicated to secure key management, some additional instructions are dedicated to easy realization of block cipher modes and cryptographic protocols in general. In the next part of the manuscript, we show that the proposed separation principles can be extended also to a processor-coprocessor architecture. We propose a secure crypto-coprocessor, which can be used in conjunction with any general-purpose processor. To demonstrate its flexibility, the crypto-coprocessor is interconnected with the NIOS II, MicroBlaze and Cortex M1 soft-core processors. In the following part of the work, we examine the resistance of the HCrypt cryptoprocessor to differential power analysis (DPA) attacks. Following this analysis, we modify the architecture of the HCrypt processor in order to simplify its protection against side channel attacks (SCA) and fault injection attacks (FIA). We show that by rearranging blocks of the HCrypt processor at macroarchitecture level, the new HCrypt2 processor becomes natively more robust to DPA and FIA. Next, we study possibilities of dynamically reconfiguring selected parts of the processor - crypto-coprocessor architecture. The dynamic reconfiguration feature can be very useful when the cipher algorithm or its implementation must be changed in response to appearance of some vulnerability. Finally, the last part of the manuscript is dedicated to thorough testing and optimizations of both versions of the HCrypt crypto-processor. Architectures of crypto-processors and crypto-coprocessors are often vulnerable to software attacks targeting the disclosure of encryption keys. The thesis introduces separation rules enabling crypto-processor/coprocessors to support secure key management. Separation rules are implemented on novel HCrypt crypto-processor resistant to software attacks targetting the disclosure of encryption keys