Power consumption of CMOS digital logic designs has increased rapidly for the last several years. It has become an important issue, not only in battery-powered applications, but also in high-performance digital designs because of packaging and cooling requirements. At multi-GHz clock rates in use today, charging and discharging CMOS gates and wires, especially in clocks with their relatively large capacitances, leads to significant power consumption. Recovering and recycling the stored charge or energy about to be lost when these nodes are discharged to ground is a potentially good strategy that must be explored for use in future energy-efficient design methodologies. This dissertation investigates a number of novel clock energy recycling techniques to improve the overall power dissipation of high-performance logic circuits. If efficient recycling energy of the clock network can be demonstrated, it might be used in many high-performance chip designs, to lower power and save energy. A number of chip prototypes were designed and constructed to demonstrate that this energy can be successfully recycled or recovered in different ways: • Recycling clock network energy by supplying a secondary DC-DC power converter: the output of this power converter can be used to supply another region of the chip, thereby avoiding the need to draw additional energy from the primary supply. One test chip demonstrates energy in the final clock load can be recycled, while another demonstrates that clock distribution energy can be recycled. • Recovering clock network energy and returning it back to the power grid: each clock cycle, a portion of the energy just drawn from the supply is transferred back at the end of the cycle, effectively reducing the power consumption of the clock network. The recycling methods described in this thesis are able to preserve the more ideal square clock shape which has been a limitation of previous work in this area. Overall, the results provided in this thesis demonstrate that energy recycling is very promising and must be pursued in a number of other areas of the chip in order to obtain an energy-efficient design.

No description available.

Power consumption of CMOS digital logic designs has increased rapidly for the last several years. It has become an important issue, not only in battery-powered applications, but also in high-performance digital designs because of packaging and cooling requirements. At multi-GHz clock rates in use today, charging and discharging CMOS gates and wires, especially in clocks with their relatively large capacitances, leads to significant power consumption. Recovering and recycling the stored charge or energy about to be lost when these nodes are discharged to ground is a potentially good strategy that must be explored for use in future energy-efficient design methodologies. This dissertation investigates a number of novel clock energy recycling techniques to improve the overall power dissipation of high-performance logic circuits. If efficient recycling energy of the clock network can be demonstrated, it might be used in many high-performance chip designs, to lower power and save energy. A number of chip prototypes were designed and constructed to demonstrate that this energy can be successfully recycled or recovered in different ways: • Recycling clock network energy by supplying a secondary DC-DC power converter: the output of this power converter can be used to supply another region of the chip, thereby avoiding the need to draw additional energy from the primary supply. One test chip demonstrates energy in the final clock load can be recycled, while another demonstrates that clock distribution energy can be recycled. • Recovering clock network energy and returning it back to the power grid: each clock cycle, a portion of the energy just drawn from the supply is transferred back at the end of the cycle, effectively reducing the power consumption of the clock network. The recycling methods described in this thesis are able to preserve the more ideal square clock shape which has been a limitation of previous work in this area. Overall, the results provided in this thesis demonstrate that energy recycling is very promising and must be pursued in a number of other areas of the chip in order to obtain an energy-efficient design.

Thesis (MS )--Montana State University--Bozeman, 2009. / Typescript. Chairperson, Graduate Committee: Hongwei Gao. Includes bibliographical references (leaves 71-73).

Thesis (M.S.)--Missouri University of Science and Technology, 2010. / Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed June 29, 2010) Includes bibliographical references (p. 95-100).

Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, June 1997. / Thesis advisor, John G. Ciezki. Includes bibliographical references (p. 97). Also available online.

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2006. / Includes bibliographical references. Also available in electronic version.

M.Ing. / Power electronic systems are often treated purely as electronic circuits. This results in manufactured systems that are electrically functional but not optimised in terms of packaging, temperature or volume. This, in turn, results in low power densities. The objective of this work is to investigate how a power converter should be built to obtain a high power density while operating at high ambient temperatures. In doing so, the parameters affecting the converter volume and thus the power density are identified. In this work, a case study is considered, comprising a DC/DC converter operating in the automotive environment. The specifications for the DC/DC converter identify the power density and high temperature operation as the primary design objectives. The DC/DC converter is implemented in the new dual voltage systems implemented in ultra-modern automobiles. An unconventional converter structure is proposed to meet the electrical and thermal specifications. The converter structure is divided into two sections, namely the active and passive components. The two components share a combined cooling structure. Each of the components is analysed fundamentally and with simulation packages on both an electrical and thermal level. The active and passive components are implemented with material technologies such as open die semiconductors on DCB substrates and high density planar inductors with specially designed cooling structures. The two components take advantage of the thermal performance of the different manufacturing technologies. The complete converter structure is implemented and evaluated both electrically and thermally. The converter structure achieves a power density of 170W/in3 while operating with a coolant temperature of 85°C. Based on the case study, techniques are developed and suggestions are made that will result in the power density and the operating temperature of the converter structure being increased. These suggestions can also be used and implemented in the design and development of any high power density and high operating temperature structure.

M.Ing. (Electrical & Electronic Engineering Science) / This study investigates the mitigation of conducted electromagnetic interference (EMI) in a flyback DC-DC converter. Without the use of filters, the maximum mitigation of EMI possible without significantly decreasing converter operating efficiency is investigated. The following parameters are found to influence EMI: · Switching speed: Decreasing switching speed (increasing rise and fall times of the MOSFET) effectively reduces both common mode (CM) and differential mode (DM) EMI above a certain frequency. Series gate resistors up to a certain value were found to not increase power dissipated in the MOSFET. Series gate resistors greater than this value, further reduce CM and DM EMI at the cost of larger amounts of power being dissipated in the MOSFET. · Leakage inductance and inter-winding capacitance: The dominant component of the flyback coupled inductor in terms of EMI generation is the inter-winding capacitance. Increasing inter-winding capacitance increases both CM and DM EMI. Reducing inter-winding capacitance increases leakage inductance. Increasing leakage inductance however, results in reduced converter efficiency. Coupled inductor design is therefore a compromise between leakage inductance and inter-winding capacitance. · Layout inductance: Reducing layout inductance in certain parts of the circuit is an effective method for reducing DM EMI. This is shown to also decrease CM EMI but not to the same extent as DM EMI. · Snubbing: Snubbing is shown to effectively reduce both CM and DM EMI by reducing the magnitude of the voltage overshoot and ringing on the drain of the MOSFET. Snubbing however reduces converter efficiency. This study gives important guidelines to the engineering trade-offs in reducing EMI versus efficiency in a flyback converter.

Power consumption of CMOS digital logic designs has increased rapidly for the last several years. It has become an important issue, not only in battery-powered applications, but also in high-performance digital designs because of packaging and cooling requirements. At multi-GHz clock rates in use today, charging and discharging CMOS gates and wires, especially in clocks with their relatively large capacitances, leads to significant power consumption. Recovering and recycling the stored charge or energy about to be lost when these nodes are discharged to ground is a potentially good strategy that must be explored for use in future energy-efficient design methodologies. This dissertation investigates a number of novel clock energy recycling techniques to improve the overall power dissipation of high-performance logic circuits. If efficient recycling energy of the clock network can be demonstrated, it might be used in many high-performance chip designs, to lower power and save energy. A number of chip prototypes were designed and constructed to demonstrate that this energy can be successfully recycled or recovered in different ways: • Recycling clock network energy by supplying a secondary DC-DC power converter: the output of this power converter can be used to supply another region of the chip, thereby avoiding the need to draw additional energy from the primary supply. One test chip demonstrates energy in the final clock load can be recycled, while another demonstrates that clock distribution energy can be recycled. • Recovering clock network energy and returning it back to the power grid: each clock cycle, a portion of the energy just drawn from the supply is transferred back at the end of the cycle, effectively reducing the power consumption of the clock network. The recycling methods described in this thesis are able to preserve the more ideal square clock shape which has been a limitation of previous work in this area. Overall, the results provided in this thesis demonstrate that energy recycling is very promising and must be pursued in a number of other areas of the chip in order to obtain an energy-efficient design. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate